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1. (WO2012176330) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/176330 International Application No.: PCT/JP2011/064542
Publication Date: 27.12.2012 International Filing Date: 24.06.2011
IPC:
G06F 13/16 (2006.01) ,G11C 11/401 (2006.01) ,H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
ルネサスエレクトロニクス株式会社 RENESAS ELECTRONICS CORPORATION [JP/JP]; 神奈川県川崎市中原区下沼部1753番地 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 2118668, JP (AllExceptUS)
松井 重純 MATSUI, Shigezumi [JP/JP]; JP (UsOnly)
諏訪 元大 SUWA, Motoo [JP/JP]; JP (UsOnly)
米田 哲 YONEDA, Satoshi [JP/JP]; JP (UsOnly)
渡辺 俊 WATANABE, Takashi [JP/JP]; JP (UsOnly)
Inventors:
松井 重純 MATSUI, Shigezumi; JP
諏訪 元大 SUWA, Motoo; JP
米田 哲 YONEDA, Satoshi; JP
渡辺 俊 WATANABE, Takashi; JP
Agent:
特許業務法人深見特許事務所 Fukami Patent Office, p.c.; 大阪府大阪市北区中之島二丁目2番7号 中之島セントラルタワー Nakanoshima Central Tower, 2-7, Nakanoshima 2-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) This semiconductor device (1) is provided with a memory controller (14) which outputs a plurality of signals (S1 to S3) which are partitioned into three groups, three switching circuits (17 to 19) which are each provided so as to correspond to the respective three groups, a plurality of buffer circuits (B1 to B3) which are partitioned into three groups, and a plurality of external terminals (TA) which are each provided so as to correspond to the respective pluralities of buffer circuits (B1 to B3). Each switching circuit imparts a plurality of signals of a corresponding group to a plurality of buffer circuits of the corresponding group in parallel in an order which corresponds to a selector control signal (SE).
(FR) L'invention porte sur un dispositif à semi-conducteur (1) qui comprend un contrôleur de mémoire (14) qui délivre une pluralité de signaux (S1 à S3) qui sont partitionnés en trois groupes, trois circuits de commutation (17 à 19) qui sont configurés chacun pour correspondre aux trois groupes respectifs, une pluralité de circuits tampon (B1 à B3) qui sont partitionnés en trois groupes, et une pluralité de bornes externes (TA) qui sont configurées chacune pour correspondre aux pluralités respectives de circuits tampon (B1 à B3). Chaque circuit de commutation communique une pluralité de signaux d'un groupe correspondant à une pluralité de circuits tampon du groupe correspondant en parallèle dans un ordre qui correspond à un signal de commande de sélecteur (SE).
(JA)  半導体装置(1)は、3つのグループに分割された複数の信号(S1~S3)を出力するメモリコントローラ(14)と、それぞれ3つのグループに対応して設けられた3個の切換回路(17~19)と、3つのグループに分割された複数のバッファ回路(B1~B3)と、それぞれ複数のバッファ回路(B1~B3)に対応して設けられた複数の外部端子(TA)とを備える。各切換回路は、対応のグループの複数の信号を、セレクタ制御信号(SE)に応じた順序で対応のグループの複数のバッファ回路に並列に与える。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2012176330