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1. (WO2012174252) OFFSET REDUCING RESISTOR CIRCUIT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/174252 International Application No.: PCT/US2012/042479
Publication Date: 20.12.2012 International Filing Date: 14.06.2012
IPC:
H01C 7/13 (2006.01) ,H01L 21/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
C
RESISTORS
7
Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
13
current-responsive
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Applicants:
ANALOG DEVICES, INC. [US/US]; One Technology Way Norwood, MA 02062-9106, US (AllExceptUS)
LIN, Yijing [CN/CN]; CN (UsOnly)
MCCARTNEY, Damien [IE/IE]; IE (UsOnly)
Inventors:
LIN, Yijing; CN
MCCARTNEY, Damien; IE
Agent:
HAILS, Robert, L.; Kenyon & Kenyon LLP 1500 K Street, N.W. Washington, DC 20005, US
Priority Data:
61/498,24417.06.2011US
Title (EN) OFFSET REDUCING RESISTOR CIRCUIT
(FR) CIRCUIT DE RÉSISTANCE À RÉDUCTION DE DÉCALAGE
Abstract:
(EN) The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type that is spaced to form respective same junction type centroids (i.e., geometric centers). The different type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit.
(FR) Les segments de résistance peuvent être placés dans une zone spatiale d'un circuit intégré. Les jonctions formées entre les segments de résistance et les conducteurs peuvent être placées à des emplacements tels que chaque jonction présente un homologue jumelé du même type espacé pour former les mêmes centroïdes respectifs du type jonction (c'est-à-dire des centres géométriques). Les centroïdes de type différent peuvent être sensiblement coïncidents, ce qui signifie que les centroïdes se chevauchent sensiblement. De cette manière, les tensions de jonction (ou tensions de décalage) produites par une paire de jonctions peuvent éliminer les tensions de jonction produites par une autre paire de jonctions dans le circuit de résistance.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)