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1. (WO2012173238) SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/173238 International Application No.: PCT/JP2012/065400
Publication Date: 20.12.2012 International Filing Date: 15.06.2012
IPC:
H01L 27/10 (2006.01) ,G11C 5/00 (2006.01) ,G11C 29/00 (2006.01) ,G11C 29/56 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/82 (2006.01) ,H01L 23/522 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
56
External testing equipment for static stores, e.g. automatic test equipment (ATE); Interfaces therefor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
東京エレクトロン株式会社 TOKYO ELECTRON LIMITED [JP/JP]; 東京都港区赤坂五丁目3番1号 3-1, Akasaka 5-chome, Minato-ku, Tokyo 1076325, JP (AllExceptUS)
岩津 春生 IWATSU, Haruo [JP/JP]; JP (UsOnly)
松本 俊行 MATSUMOTO, Toshiyuki [JP/JP]; JP (UsOnly)
Inventors:
岩津 春生 IWATSU, Haruo; JP
松本 俊行 MATSUMOTO, Toshiyuki; JP
Agent:
金本 哲男 KANEMOTO, Tetsuo; 東京都新宿区住吉町1-20 角張ビル はづき国際特許事務所 Hazuki International, Kakubari Building, 1-20, Sumiyoshi-cho, Shinjuku-ku, Tokyo 1620065, JP
Priority Data:
2011-13527317.06.2011JP
2011-13527617.06.2011JP
2011-13527917.06.2011JP
Title (EN) SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEURS ET DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置の製造方法及び半導体装置
Abstract:
(EN) A manufacturing method for a semiconductor device includes: a through-hole formation step for forming an electrode through-hole which passes through a substrate on which a circuit has been formed, in the thickness direction; a through-electrode formation step for forming a through-electrode by supplying a conductive material to the through-hole for an electrode; a step for forming wiring at least a portion of which is exposed on the surface of the substrate and which is connected to the circuit but not to the through-electrode; a selective connection step which does not electrically connect the through-electrode to the wiring when the circuit is deemed to be defective in an electrical test of the circuit, and which electrically connects the through-electrode to the wiring by applying conductive material when the circuit is deemed to be good in an electrical test of the circuit; and a stacking step for stacking a plurality of substrates in which the through-electrode and the wiring have been formed.
(FR) L'invention concerne un procédé de fabrication pour un dispositif à semi-conducteurs, qui comprend : une étape de formation de trou traversant consistant à former un trou traversant pour électrode qui traverse un substrat sur lequel a été formé un circuit, dans la direction de l'épaisseur ; une étape de formation d'électrode traversante, consistant à former une électrode traversante par introduction d'un matériau conducteur dans le trou traversant pour électrode ; une étape consistant à former un câblage dont au moins une partie est exposée sur la surface du substrat et qui est connecté au circuit mais n'est pas connecté à l'électrode traversante ; une étape de connexion sélective qui ne connecte pas électriquement l'électrode traversante au câblage lorsque le circuit est considéré comme étant défectueux dans un essai électrique du circuit, et qui connecte électriquement l'électrode traversante au câblage par application d'un matériau conducteur lorsque le circuit est considéré comme étant bon dans un essai électrique du circuit ; et une étape d'empilage consistant à empiler une pluralité de substrats dans lesquels l'électrode traversante et le câblage ont été formés.
(JA)  半導体装置の製造方法は、回路が形成された基板の厚み方向に貫通する、電極用貫通孔を形成する貫通孔形成工程と、前記電極用貫通孔に導電性材料を供給して、貫通電極を形成する貫通電極形成工程と、前記回路には接続されて、前記貫通電極には接続されておらず、少なくとも一部が前記基板の表面に露出している配線を形成する工程と、前記回路の電気的試験の結果、不良品と判定された不良品回路においては、前記貫通電極と前記配線とを電気的に接続せず、前記回路の電気的試験の結果、良品と判定された良品回路においては、導電性材料で接合することにより、前記貫通電極と前記配線とを電気的に接続する選択的接続工程と、前記貫通電極及び前記配線が形成された基板を複数積層する積層工程と、を有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2012173238KR1020140040745