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1. (WO2012172976) SEMICONDUCTOR INTEGRATED DEVICE, DISPLAY DEVICE, AND DEBUGGING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/172976 International Application No.: PCT/JP2012/063874
Publication Date: 20.12.2012 International Filing Date: 30.05.2012
IPC:
G09G 3/36 (2006.01) ,G01R 31/28 (2006.01) ,G06F 11/28 (2006.01) ,G09G 3/20 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
28
by checking the correct order of processing
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府大阪市阿倍野区長池町22番22号 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
横沼 真介 YOKONUMA, Shinsuke; null (UsOnly)
Inventors:
横沼 真介 YOKONUMA, Shinsuke; null
Agent:
島田 明宏 SHIMADA, Akihiro; 奈良県橿原市八木町1丁目10番3号 萬盛庵ビル 島田特許事務所 Shimada Patent Firm, Manseian Building, 1-10-3, Yagi-cho, Kashihara-shi, Nara 6340078, JP
Priority Data:
2011-13489817.06.2011JP
Title (EN) SEMICONDUCTOR INTEGRATED DEVICE, DISPLAY DEVICE, AND DEBUGGING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE
(FR) DISPOSITIF INTÉGRÉ À SEMI-CONDUCTEURS, DISPOSITIF D'AFFICHAGE ET PROCÉDÉ DE DÉBOGAGE POUR DISPOSITIF INTÉGRÉ À SEMI-CONDUCTEURS
(JA) 半導体集積装置、表示装置、および半導体集積装置のデバッグ方法
Abstract:
(EN) Provided is a semiconductor integrated device that matches high-speed serial interface specifications, is low cost, and can easily be debugged. In an LCD driver (20), a display control circuit side DSI interface (211) and display control circuit side single end interface (212) are provided. A debug mode 0 command is issued by a DSI bus (L1) connected to the display control circuit side DSI interface (211), and preparations are made for connecting a test device (500) to a single end bus (L2) connected to the display control circuit side single end interface (212). Thereafter, the operating mode for a display control circuit (200) transitions to a debug mode by the issuing of a debug mode ON command by the DSI bus (L1). In the debug mode, debugging is carried out using a signal that is transmitted in the single end bus (L2).
(FR) L'invention concerne un dispositif intégré à semi-conducteurs qui satisfait aux spécifications des interfaces série rapides, qui est économique et qui peut être débogué facilement. Dans un pilote (20) de LCD, un circuit de commande d'affichage comprend une interface DSI (211) côté circuit de commande d'affichage et une interface (212) à extrémité unique côté circuit de commande d'affichage. Une commande 0 de mode de débogage est émise par un bus DSI (L1) relié à l'interface DSI (211) côté circuit de commande d'affichage, et des préparations sont effectuées pour relier un dispositif d'essai (500) à un bus à extrémité unique (L2) relié à l'interface (212) à extrémité unique côté circuit de commande d'affichage. Le mode de fonctionnement d'un circuit de commande d'affichage (200) passe ensuite à un mode de débogage lors de l'émission d'une instruction d'activation de mode de débogage par le bus DSI (L1). En mode débogage, le débogage est effectué au moyen d'un signal qui est émis sur le bus à extrémité unique (L2).
(JA)  高速シリアルインターフェース規格に対応した、低コストかつ容易にデバッグが可能な半導体集積装置を提供する。 LCDドライバ(20)には、表示制御回路側DSIインターフェース(211)および表示制御回路側シングルエンドインターフェース(212)が設けられている。表示制御回路側DSIインターフェース(211)に接続されたDSIバス(L1)で、デバッグモード0コマンドが発行され、表示制御回路側シングルエンドインターフェース(212)に接続されたシングルエンドバス(L2)に検査デバイス(500)を接続するための準備がなされる。その後、DSIバス(L1)でデバッグモードONコマンドが発行されることにより、表示制御回路(200)の動作モードがデバッグモードに移行する。デバッグモードでは、シングルエンドバス(L2)を伝送する信号を用いてデバッグが行われる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20140085353