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1. (WO2012169397) THIN-FILM TRANSISTOR, METHOD FOR PRODUCING SAME, AND DISPLAY ELEMENT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/169397 International Application No.: PCT/JP2012/063877
Publication Date: 13.12.2012 International Filing Date: 30.05.2012
IPC:
H01L 29/786 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府大阪市阿倍野区長池町22番22号 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
冨田 雅裕 TOMIDA, Masahiro; null (UsOnly)
北角 英人 KITAKADO, Hidehito; null (UsOnly)
冨安 一秀 TOMIYASU, Kazuhide; null (UsOnly)
加藤 純男 KATOH, Sumio; null (UsOnly)
Inventors:
冨田 雅裕 TOMIDA, Masahiro; null
北角 英人 KITAKADO, Hidehito; null
冨安 一秀 TOMIYASU, Kazuhide; null
加藤 純男 KATOH, Sumio; null
Agent:
島田 明宏 SHIMADA, Akihiro; 奈良県橿原市八木町1丁目10番3号 萬盛庵ビル 島田特許事務所 Shimada Patent Firm, Manseian Building, 1-10-3, Yagi-cho, Kashihara-shi, Nara 6340078, JP
Priority Data:
2011-12693707.06.2011JP
Title (EN) THIN-FILM TRANSISTOR, METHOD FOR PRODUCING SAME, AND DISPLAY ELEMENT
(FR) TRANSISTOR À COUCHE MINCE, SON PROCÉDÉ DE PRODUCTION, ET ÉLÉMENT D'AFFICHAGE
(JA) 薄膜トランジスタ、その製造方法、および表示素子
Abstract:
(EN) A semiconductor layer (40) is formed from an oxide semiconductor in which the width of a channel region (40a) is smaller than the widths of source and drain electrodes (60a, 60b) and the area of the side surface is enlarged. The semiconductor layer (40) is sandwiched between a gate insulating film (30) and a passivation film (90) and is subjected to annealing in an atmosphere containing oxygen. As a consequence, external oxygen and the oxygen contained in the gate insulating film (30) and the passivation film (90) are supplied to the channel region (40a), the areas of low-resistance regions (40b) become small, and the region sandwiched by the two low-resistance regions (40b) becomes a high-resistance region (40c). Meanwhile, the contact resistance between the semiconductor layer (40) and the source and drain electrodes (60a, 60b) are kept low. As a result, the on and off ratio becomes large and suitable transistor properties are obtained.
(FR) Une couche semi-conductrice (40) est formée à partir d'un semi-conducteur oxyde dans lequel la largeur d'une zone de canal (40a) est inférieure aux largeurs d'électrodes de source et de drain (60a, 60b) et l'aire de la surface latérale est élargie. La couche semi-conductrice (40) est intercalée entre une pellicule d'isolation de gâchette (30) et une pellicule de passivation (90) et est soumise à un recuit dans une atmosphère contenant de l'oxygène. En conséquence, l'oxygène externe et l'oxygène contenu dans la pellicule d'isolation de gâchette (30) et la pellicule de passivation (90) sont fournis à la zone de canal (40a), les aires de zones à faible résistance (40b) deviennent petites, et la zone intercalée entre les deux zones à faible résistance (40b) devient une zone à résistance élevée (40c). En même temps, la résistance de contact entre la couche semi-conductrice (40) et les électrodes de source et de drain (60a, 60b) est maintenue basse. Ainsi, le ratio d'activation et de désactivation devient large et des propriétés de transistor convenables sont obtenues.
(JA)  チャネル領域(40a)の幅を、ソース/ドレイン電極(60a、60b)の幅よりも狭くして、側面の面積を大きくした酸化物半導体からなる半導体層(40)を、ゲート絶縁膜(30)とパッシベーション膜(90)とで挟み、酸素を含む雰囲気中でアニールする。これにより、外部からの酸素と、ゲート絶縁膜(30)およびパッシベーション膜(90)に含まれる酸素がチャネル領域(40a)に供給され、低抵抗領域(40b)の面積が狭くなり、2つの低抵抗領域(40b)に挟まれた領域は高抵抗領域(40c)になる。一方、ソース/ドレイン電極(60a、60b)と半導体層(40)とのコンタクト抵抗は低く保たれる。その結果、オン・オフ比が大きくなり、良好なトランジスタ特性が得られる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)