Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2012166732) METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/166732 International Application No.: PCT/US2012/039860
Publication Date: 06.12.2012 International Filing Date: 29.05.2012
IPC:
H01L 21/265 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/26 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
Applicants:
APPLIED MATERIALS, INC. [US/US]; 3050 Bowers Avenue Santa Clara, CA 95054, US (AllExceptUS)
HUANG, Yi-Chiau [CN/US]; US (UsOnly)
SANCHEZ, Errol [US/US]; US (UsOnly)
TAO, Xianzhi [US/US]; US (UsOnly)
Inventors:
HUANG, Yi-Chiau; US
SANCHEZ, Errol; US
TAO, Xianzhi; US
Agent:
PATTERSON, B. Todd; Patterson & Sheridan, L.L.P. 3040 Post Oak Blvd., Suite 1500 Houston, Texas 77056-6582, US
Priority Data:
61/493,26403.06.2011US
Title (EN) METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE
(FR) PROCÉDÉ DE FORMATION D'UNE COUCHE DE GERMANIUM DE FAIBLE RÉSISTIVITÉ À UNE VITESSE DE CROISSANCE ÉLEVÉE SUR UN SUBSTRAT EN SILICIUM
Abstract:
(EN) A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium.
(FR) L'invention porte sur un procédé de formation d'une couche de semi-conducteur dopée sur un substrat. Une couche de base ayant une structure cristalline compatible avec une structure cristalline thermodynamiquement favorisée de la couche de semi-conducteur dopée est formée sur le substrat et recuite, ou recuite en surface, pour faire cristalliser en grande partie la surface de la couche de base. La couche de semi-conducteur dopée est formée sur la couche de base. Chaque couche peut être formée par des procédés de dépôt en phase vapeur tels qu'un procédé de dépôt CVD. La couche de base peut être du germanium et la couche de semi-conducteur dopée peut être du germanium dopé par du phosphore.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)