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1. WO2012145480 - REINFORCED FAN-OUT WAFER-LEVEL PACKAGE

Publication Number WO/2012/145480
Publication Date 26.10.2012
International Application No. PCT/US2012/034203
International Filing Date 19.04.2012
IPC
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
H01L 21/56 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
H01L 23/538 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/683 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683for supporting or gripping
H01L 25/10 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10the devices having separate containers
CPC
H01L 21/568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
568Temporary substrate used as encapsulation process aid
H01L 2224/12105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
H01L 2224/73267
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73267Layer and HDI connectors
H01L 2225/1035
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2225Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
10the devices having separate containers
1005the devices being of a type provided for in group H01L27/00
1011the containers being in a stacked arrangement
1017the lowermost container comprising a device support
1035the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
H01L 2225/1058
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2225Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
10the devices having separate containers
1005the devices being of a type provided for in group H01L27/00
1011the containers being in a stacked arrangement
1047Details of electrical connections between containers
1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
H01L 23/3128
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
3121a substrate forming part of the encapsulation
3128the substrate having spherical bumps for external connection
Applicants
  • TESSERA, INC. [US]/[US] (AllExceptUS)
  • HABA, Belgacem [US]/[US] (UsOnly)
  • KANG, Teck-gyu [KR]/[US] (UsOnly)
Inventors
  • HABA, Belgacem
  • KANG, Teck-gyu
Agents
  • HAGES, Michael, T.
Priority Data
13/091,74421.04.2011US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) REINFORCED FAN-OUT WAFER-LEVEL PACKAGE
(FR) ENCAPSULATION SUR TRANCHE, ÉCARTÉE EN ÉVENTAIL ET RENFORCÉE
Abstract
(EN)
A microelectronic package (10) includes a microelectronic element (12) including a first surface (14) having contacts (28) thereon, a second surface (16) remote therefrom, and edge surfaces (24) extending between the first and second surfaces. A reinforcing layer (50) adheres to the at least one edge surface (24) and extends in a direction away therefrom, the reinforcing layer (50) not extending along the first surface (14) of the microelectronic element (12). A conductive redistribution layer (30) including a plurality of conductive elements (34) extends from the contacts (28) along the first surface (14) and along a surface (54) of the reinforcing layer (50) beyond the at least one edge surface (24). An encapsulant (18) overlies at least the reinforcing layer (50). The microelectronic element (12) has a first coefficient of thermal expansion, the encapsulant (18) has a second coefficient of thermal expansion, and the reinforcing layer (50) has a third coefficient of thermal expansion that is between the first and second coefficients of thermal expansion.
(FR)
La présente invention concerne une encapsulation microélectronique (10) qui comprend un élément microélectronique (12) qui comporte une première surface (14) sur laquelle se trouvent des contacts (28), une seconde surface (16) éloignée de ladite première surface, et des surfaces de bord (24) qui s'étendent entre les première et seconde surfaces. Une couche de renforcement (50) adhère à la ou aux surfaces de bord (24) et s'étend dans une direction pour s'en éloigner, la couche de renforcement (50) ne s'étendant pas le long de la première surface (14) de l'élément microélectronique (12). Une couche de redistribution conductrice (30) qui comprend une pluralité d'éléments conducteurs (34) s'étend à partir des contacts (28) le long de la première surface (14) et le long d'une surface (54) de la couche de renforcement (50) au-delà de la ou des surfaces de bord (24). Un encapsulant (18) recouvre au moins la couche de renforcement (50). L'élément microélectronique (12) possède un premier coefficient de dilatation thermique, l'encapsulant (18) possède un deuxième coefficient de dilatation thermique, et la couche de renforcement (50) possède un troisième coefficient de dilatation thermique qui se trouve entre les premier et deuxième coefficients de dilatation thermique.
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