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1. WO2012143325 - METHOD FOR ETCHING A BST LAYER

Publication Number WO/2012/143325
Publication Date 26.10.2012
International Application No. PCT/EP2012/056901
International Filing Date 16.04.2012
IPC
H01L 21/311 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105After-treatment
311Etching the insulating layers
CPC
H01G 7/06
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
7Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
06having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors
H01L 21/31111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
H01L 28/55
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
28Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
40Capacitors
55with a dielectric comprising a perovskite structure material
Applicants
  • STMICROELECTRONICS (TOURS) SAS [FR]/[FR] (AllExceptUS)
  • STMICROELECTRONICS S.R.L. [IT]/[IT] (AllExceptUS)
  • CARO, Vincent [FR]/[FR] (UsOnly)
  • RODILOSSO, Davide [IT]/[IT] (UsOnly)
Inventors
  • CARO, Vincent
  • RODILOSSO, Davide
Agents
  • CABINET BEAUMONT
Priority Data
11305473.820.04.2011EP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR ETCHING A BST LAYER
(FR) PROCÉDÉ DE GRAVURE D'UNE COUCHE DE BST
Abstract
(EN)
The invention concerns a method for etching a PVD deposited barium strontium titanate (BST) layer, wherein a non-ionic surfactant at a concentration between 0.1 and 1 percent is added to an acid etching solution.
(FR)
L'invention concerne un procédé de gravure d'une couche de titanate de baryum et de strontium (BST) déposée par PVD, dans lequel un tensioactif non ionique à une concentration comprise entre 0,1 et 1 % est ajouté à une solution de gravure à l'acide.
Latest bibliographic data on file with the International Bureau