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Pub. No.: WO/2012/124677 International Application No.: PCT/JP2012/056373
Publication Date: 20.09.2012 International Filing Date: 13.03.2012
IPC:
H01L 27/08 (2006.01) ,H01L 21/822 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 27/04 (2006.01) ,H01L 27/088 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
Applicants: YAMAJI, Masaharu[JP/JP]; JP (UsOnly)
FUJI ELECTRIC CO., LTD.[JP/JP]; 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP (AllExceptUS)
Inventors: YAMAJI, Masaharu; JP
Agent: SAKAI, Akinori; A. SAKAI & ASSOCIATES 20F, Kasumigaseki Building 2-5, Kasumigaseki 3-chome Chiyoda-ku, Tokyo 1006020, JP
Priority Data:
2011-05657715.03.2011JP
Title (EN) HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ HAUTE TENSION
(JA) 高耐圧集積回路装置
Abstract:
(EN) A high-voltage integrated circuit device (100) is provided with an n region (3), which is a high-side floating potential region, an n- region (4) that forms a high-voltage junction terminal region (93), and an n- region (2), which is a LVDD potential region, on a surface layer of a p semiconductor substrate (1). A low-side circuit part (91) is disposed on the n- region (2). A universal contact region (58) that makes ohmic contact is disposed beneath a pickup electrode (59), which is disposed on the high-voltage junction terminal region (93). The universal contact region (58) has a constitution in which p+ regions (56) and n+ regions (57) are in alternating contact following along the surface of the p semiconductor substrate (1). By disposing the universal contact region (58) thusly, the amount of carriers flowing into the low-side circuit part (91) can be reduced when a negative surge voltage is input. Thus, erroneous operation of the logic part of the low-side circuit part (91) and latching up of the low-side circuit part (91) can be prevented.
(FR) L'invention concerne un dispositif de circuit intégré haute tension (100) comprenant une région n (3) qui est une région à potentiel flottant côté haut, une région n- (4) formant une région de borne de jonction haute tension (93) et une région n- (2) qui est une région à potentiel BFCC, sur une couche de surface d'un substrat semi-conducteur p (1). Une partie de circuit côté bas (91) est disposée sur la région n- (2). Une région de contact universelle (58) assurant un contact ohmique est disposée en dessous d'une électrode de collecte (59), qui est disposée sur la région de borne de jonction haute tension (93). La région de contact universelle (58) est telle que les régions p+ (56) et les régions n+ (57) sont alternativement en contact le long de la surface du substrat semi-conducteur p (1). En disposant la région de contact universelle (58) de cette manière, il est possible de diminuer la quantité de supports dans la partie circuit côté bas (92) lorsqu'une tension pic négative est entrée. Il est ainsi possible d'éviter tout dysfonctionnement de la partie logique de la partie circuit côté bas (91) ainsi que le verrouillage de la partie circuit côté bas (91).
(JA)  高耐圧集積回路装置(100)は、p半導体基板(1)の表面層に、ハイサイド浮遊電位領域であるn領域(3)と、高耐圧接合終端領域(93)となるn-領域(4)と、L-VDD電位領域であるn-領域(2)とを備える。ローサイド回路部(91)は、n-領域(2)に配置される。高耐圧接合終端領域(93)に配置されたピックアップ電極(59)下には、オーミック接触するユニバーサルコンタクト領域(58)が配置される。ユニバーサルコンタクト領域(58)は、p半導体基板(1)の表面に沿ってp+領域(56)とn+領域(57)とが交互に接する構成を有する。このようにユニバーサルコンタクト領域(58)を配置することで、負サージ電圧が入力された場合に、ローサイド回路部(91)に流れ込むキャリア量を低減することができる。これにより、ローサイド回路部(91)のロジック部の誤動作やラッチアップによる破壊を防止することができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)