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1. (WO2012124281) METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE, THIN-FILM TRANSISTOR SUBSTRATE MANUFACTURED BY SAME, AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2012/124281 International Application No.: PCT/JP2012/001468
Publication Date: 20.09.2012 International Filing Date: 02.03.2012
IPC:
H01L 29/786 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01)
Applicants: ODA, Akihiro; null (UsOnly)
MATSUKIZONO, Hiroshi; null (UsOnly)
SHARP KABUSHIKI KAISHA[JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
Inventors: ODA, Akihiro; null
MATSUKIZONO, Hiroshi; null
Agent: MAEDA & PARTNERS; Osaka-Marubeni Bldg.5F 5-7, Hommachi 2-chome Chuo-ku, Osaka-shi Osaka 5410053, JP
Priority Data:
2011-05462411.03.2011JP
Title (EN) METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE, THIN-FILM TRANSISTOR SUBSTRATE MANUFACTURED BY SAME, AND DISPLAY DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN SUBSTRAT DE TRANSISTOR EN COUCHES MINCES, SUBSTRAT DE TRANSISTOR EN COUCHES MINCES FABRIQUÉ GRÂCE À CELUI-CI ET DISPOSITIF D'AFFICHAGE
(JA) 薄膜トランジスタ基板の製造方法およびその方法により製造された薄膜トランジスタ基板、表示装置
Abstract: front page image
(EN) A method for manufacturing a thin-film transistor substrate, comprising: a step of forming a gate electrode (11aa) on an insulating substrate (10a); a step of forming a first gate insulating layer (12a) comprising a silicon nitride film so as to cover the gate electrode (11a), and subsequently supplying an oxygen radical to a front surface of the first gate insulating layer (12a) to conduct a surface treatment; a step of forming a second gate insulating layer (12b) comprising a silicon oxide film on the first gate insulating layer (12a); and a step of forming an oxide semiconductor layer (12a) on the second gate insulating layer (12b).
(FR) L'invention concerne un procédé de fabrication d'un substrat de transistor en couches minces comprenant : une étape de formation d'une électrode de grille (11aa) sur un substrat isolant (10a) ; une étape de formation d'une première couche isolante de grille (12a) comprenant un film de nitrure de silicium afin de couvrir l'électrode de grille (11a), et de fourniture par la suite d'un radical oxygène à une surface avant de la première couche isolante de grille (12a) pour effectuer un traitement de surface ; une étape de formation d'une seconde couche isolante de grille (12b) comprenant un film d'oxyde de silicium sur la première couche isolante de grille (12a) ; et une étape de formation d'une couche semi-conductrice d'oxyde (12a) sur la seconde couche isolante de grille (12b).
(JA)  薄膜トランジスタ基板の製造方法あって、絶縁基板(10a)上にゲート電極(11aa)を形成する工程と、ゲート電極(11a)を覆うように窒化シリコン膜からなる第1ゲート絶縁層(12a)を形成した後、第1ゲート絶縁層(12a)の表面に対して酸素ラジカルを供給して表面処理を行い、第1ゲート絶縁層(12a)上に酸化シリコン膜からなる第2ゲート絶縁層(12b)を形成する工程と、第2ゲート絶縁層(12b)上に酸化物半導体層(12a)を形成する工程とを備える。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)