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Machine translation
1. (WO2012121113) ELECTRONIC CIRCUIT SUBSTRATE, DISPLAY DEVICE, AND WIRING SUBSTRATE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2012/121113 International Application No.: PCT/JP2012/055266
Publication Date: 13.09.2012 International Filing Date: 01.03.2012
IPC:
H01L 21/60 (2006.01) ,G02F 1/1345 (2006.01) ,G09F 9/00 (2006.01) ,H05K 3/32 (2006.01)
Applicants: MATSUI Takashi; null (UsOnly)
SHIOTA Motoji; null (UsOnly)
NAKAHAMA Hiroki; null (UsOnly)
SHARP KABUSHIKI KAISHA[JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
Inventors: MATSUI Takashi; null
SHIOTA Motoji; null
NAKAHAMA Hiroki; null
Agent: OKUDA Seiji; OKUDA & ASSOCIATES, 10th Floor, Osaka Securities Exchange Bldg., 8-16, Kitahama 1-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP
Priority Data:
2011-04745204.03.2011JP
Title (EN) ELECTRONIC CIRCUIT SUBSTRATE, DISPLAY DEVICE, AND WIRING SUBSTRATE
(FR) SUBSTRAT DE CIRCUIT ÉLECTRONIQUE, DISPOSITIF D'AFFICHAGE ET SUBSTRAT DE CÂBLAGE
(JA) 電子回路基板、表示装置および配線基板
Abstract: front page image
(EN) A wiring substrate (11) comprises: a substrate; and, formed upon the substrate, a plurality of wires, a plurality of circuit elements, and a plurality of connection terminals (51) connected via the plurality of wires. Each of the plurality of connection terminals (51) further comprises a pair of protrusion parts (50), forming a depression part (60) between the pair of protrusion parts (50), and a depression electrode (52) which is disposed in the depression part (60) and which at least partially covers each pair of protrusion parts (50).
(FR) Cette invention concerne un substrat de câblage (11), comprenant : un substrat ainsi qu'une pluralité de fils de câblage, une pluralité d'éléments de circuit et une pluralité de bornes de connexion (51) connectées via la pluralité de fils de câblage. Chacune desdites bornes de connexion (510) comprend en outre une paire de parties saillantes (50) formant une partie creuse (60) entre la paire de parties saillantes (50), ainsi qu'une électrode de partie creuse (52) disposée dans la partie creuse (60) et recouvrant au moins partiellement chaque paire de parties saillantes (50).
(JA)  配線基板(11)は、基板と、基板上に形成された、複数の配線、複数の回路素子、および複数の配線を介して接続された複数の接続端子(51)とを備えている。複数の接続端子(51)のそれぞれは、一対の凸部(50)であって、それらの間に凹部(60)を形成する一対の凸部(50)と、凹部(60)において設けられ、一対の凸部(50)のそれぞれの少なくとも一部を覆う凹部電極(52)とを有する。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)