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1. (WO2012117745) SEMICONDUCTOR SUBSTRATE AND METHOD OF PRODUCING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2012/117745 International Application No.: PCT/JP2012/001477
Publication Date: 07.09.2012 International Filing Date: 02.03.2012
IPC:
H01L 29/786 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants: AOKI, Takeshi[JP/JP]; JP (UsOnly)
YAMADA, Hisashi[JP/US]; US (UsOnly)
FUKUHARA, Noboru[JP/JP]; JP (UsOnly)
HATA, Masahiko[JP/JP]; JP (UsOnly)
YOKOYAMA, Masafumi[JP/JP]; JP (UsOnly)
KIM, SangHyeon[KR/JP]; JP (UsOnly)
TAKENAKA, Mitsuru[JP/JP]; JP (UsOnly)
TAKAGI, Shinichi[JP/JP]; JP (UsOnly)
YASUDA, Tetsuji[JP/JP]; JP (UsOnly)
SUMITOMO CHEMICAL COMPANY, LIMITED[JP/JP]; 27-1, Shinkawa 2-chome, Chuo-ku, Tokyo 1048260, JP (AllExceptUS)
THE UNIVERSITY OF TOKYO[JP/JP]; 3-1, Hongo 7-chome, Bunkyo-ku, Tokyo 1138654, JP (AllExceptUS)
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY[JP/JP]; 3-1, Kasumigaseki 1-chome, Chiyoda-ku, Tokyo 1008921, JP (AllExceptUS)
Inventors: AOKI, Takeshi; JP
YAMADA, Hisashi; US
FUKUHARA, Noboru; JP
HATA, Masahiko; JP
YOKOYAMA, Masafumi; JP
KIM, SangHyeon; JP
TAKENAKA, Mitsuru; JP
TAKAGI, Shinichi; JP
YASUDA, Tetsuji; JP
Agent: RYUKA IP LAW FIRM; 22F, Shinjuku L Tower 6-1, Nishi-Shinjuku 1-chome Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2011-04551002.03.2011JP
Title (EN) SEMICONDUCTOR SUBSTRATE AND METHOD OF PRODUCING SAME
(FR) SUBSTRAT SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体基板及びその製造方法
Abstract:
(EN) The purpose of the present invention is to a provide a transistor in which damage received by a semiconductor layer during lamination by a DWB method is reduced, the effects of received damage and the effects of the interface state are minimized, and high carrier mobility is maintained. The present invention provides a semiconductor substrate having a base substrate (102), a first insulating layer (104), and a semiconductor layer (106). The first insulating layer (104) comprises an amorphous metal oxide or amorphous metal nitride. The semiconductor layer (106) includes a first crystal layer (108) and a second crystal layer (110), the electron affinity Ea1 of the first crystal layer (108) being greater than the electron affinity Ea2 of the second crystal layer (110).
(FR) La présente invention a pour but de proposer un transistor dans lequel un dommage reçu par une couche de semi-conducteur pendant une stratification par un procédé DWB est réduit, les effets d'un dommage reçu et les effets de l'état d'interface sont rendus minimaux, et une mobilité élevée des porteurs de charge est maintenue. La présente invention propose un substrat semi-conducteur ayant un substrat de base (102), une première couche isolante (104) et une couche de semi-conducteur (106). La première couche isolante (104) comprend un oxyde métallique amorphe ou un nitrure métallique amorphe. La couche de semi-conducteur (106) comprend une première couche cristalline (108) et une seconde couche cristalline (110), l'affinité électronique Ea1 de la première couche cristalline (108) étant supérieure à l'affinité électronique Ea2 de la seconde couche cristalline (110).
(JA)  本発明は、DWB法における貼り合わせ時に、半導体層が受けるダメージを小さくし、受けたダメージの影響及び界面準位の影響を低く抑え、高いキャリア移動度を有するトランジスタを提供することを目的とする。 本発明は、ベース基板(102)と第1絶縁体層(104)と半導体層(106)とを有し、第1絶縁体層(102)が、アモルファス状金属酸化物またはアモルファス状金属窒化物からなり、半導体層(106)が、第1結晶層(108)および第2結晶層(110)を含み、第1結晶層(108)の電子親和力Ea1が、第2結晶層(110)の電子親和力Ea2より大きい半導体基板を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)