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Machine translation
1. (WO2012116006) PIPELINED ADC INTER-STAGE ERROR CALIBRATION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/116006    International Application No.:    PCT/US2012/026022
Publication Date: 30.08.2012 International Filing Date: 22.02.2012
IPC:
H03M 1/10 (2006.01), H03M 1/12 (2006.01)
Applicants: TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474 (US) (For All Designated States Except US).
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-shinjuku 6-chome Shinjuku-ku, Tokyo, 160-8366 (JP) (JP only).
SHI, Kun [CN/US]; (US) (For US Only).
SESTOK, Charles [US/US]; (US) (For US Only).
SATARZADEH, Patrick [US/US]; (US) (For US Only).
REDFERN, Arthur, J. [US/US]; (US) (For US Only)
Inventors: SHI, Kun; (US).
SESTOK, Charles; (US).
SATARZADEH, Patrick; (US).
REDFERN, Arthur, J.; (US)
Agent: FRANZ, Warren, L.; Texas Instruments Incorporated Deputy General Patent Counsel P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474 (US)
Priority Data:
13/032,457 22.02.2011 US
Title (EN) PIPELINED ADC INTER-STAGE ERROR CALIBRATION
(FR) CALIBRAGE D'ERREURS INTER-ÉTAGES POUR CONVERTISSEUR ANALOGIQUE-NUMÉRIQUE DE TYPE PIPELINE
Abstract: front page image
(EN)An analog-to-digital converter (ADC) (200) includes a plurality of pipelined ADCs (202-1, 202-2) and an adjustment circuit (204). Each pipelined ADC is adapted to receive an analog input signal (AIN) and to generate an output signal (Da, Db) for an output circuit (206), has an adjustable transfer function, and includes a compensator. The adjustment circuit (204) is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.
(FR)Cette invention concerne un convertisseur analogique-numérique (CAN) (200) comprenant une pluralité de CAN de type pipeline (202-1, 202-2) et un circuit d'ajustement (204). Chaque CAN de type pipeline est conçu pour recevoir un signal d'entrée analogique (AIN) et pour générer un signal de sortie (Da, Db) pour un circuit de sortie (206). De plus, chaque CAN est doté d'une fonction de transfert ajustable et comprend un compensateur. Ledit circuit d'ajustement (204) est couplé à chaque CAN de type pipeline pour permettre l'ajustement de la fonction de transfert pour chaque CAN de type pipeline de façon à éliminer généralement une ambiguïté d'estimation. En outre, le circuit d'ajustement estime une erreur inter-étages qui comprend au moins une erreur de gain inter-étages et une erreur de gain de CAN, et ajuste le compensateur pour chaque CAN de type pipeline pour compenser l'erreur inter-étages.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)