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Machine translation
1. (WO2012115840) DELAY FAULT TESTING FOR CHIP I/O
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/115840    International Application No.:    PCT/US2012/025311
Publication Date: 30.08.2012 International Filing Date: 15.02.2012
IPC:
G01R 31/3183 (2006.01)
Applicants: RAMBUS INC. [US/US]; 1050 Enterprise Way, Suite 700 Sunnyvale, CA 94089 (US) (For All Designated States Except US).
FRANZON, Paul, D. [US/US]; (US) (For US Only)
Inventors: FRANZON, Paul, D.; (US)
Agent: SCHUYLER, Marc P.; Law Office of Marc P. Schuyler PO Box 2535 Saratoga, CA 95070 (US)
Priority Data:
61/446,386 24.02.2011 US
Title (EN) DELAY FAULT TESTING FOR CHIP I/O
(FR) DÉTECTION DE PROBLÈME DE RETARD POUR DES E/S DE PUCE
Abstract: front page image
(EN)An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.
(FR)La présente invention se rapporte à une puce de circuit intégré (IC). La puce IC comprend une sortie de signal via laquelle un signal de sortie est transmis, et une entrée de signal via laquelle un signal d'entrée est reçu. La puce IC comprend d'autre part un circuit de passage adapté pour coupler la sortie de signal à l'entrée de signal tandis que puce de circuit intégré est testée. Par ailleurs, un circuit à retard produit un premier signal de rythme et un second signal de rythme tandis que puce de circuit intégré est testée. Le second signal de rythme est retardé par rapport au premier signal de rythme sur la base d'un paramètre de test. Le premier signal de rythme déclenche la transmission d'un signal de test via la sortie de signal, et le second signal de rythme déclenche l'échantillonnage du signal de test reçu via l'entrée de signal.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)