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1. (WO2012113898) ELECTRONIC COMPONENT AND PROCESS FOR FABRICATING AND USING GRAPHENE IN AN ELECTRONIC COMPONENT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/113898    International Application No.:    PCT/EP2012/053127
Publication Date: 30.08.2012 International Filing Date: 24.02.2012
IPC:
H01L 29/16 (2006.01), H01L 29/66 (2006.01), H01L 29/78 (2006.01)
Applicants: THALES [FR/FR]; 45 rue de Villiers F-92200 Neuilly Sur Seine (FR) (For All Designated States Except US).
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (C.N.R.S.) [FR/FR]; 3 rue Michel Ange F-75016 Paris (FR) (For All Designated States Except US).
UNIVERSITE PARIS-SUD [FR/FR]; 15, rue Georges Clémenceau F-91400 Orsay (FR) (For All Designated States Except US).
SENEOR, Pierre [FR/FR]; (FR) (For US Only).
DLUBAK, Bruno [FR/FR]; (FR) (For US Only).
BARRAUD, Clément [FR/FR]; (FR) (For US Only).
TATAY-AGUILAR, Sergio [ES/FR]; (FR) (For US Only)
Inventors: SENEOR, Pierre; (FR).
DLUBAK, Bruno; (FR).
BARRAUD, Clément; (FR).
TATAY-AGUILAR, Sergio; (FR)
Agent: JACOBSON, Claude; Cabinet Lavoix 2, place d'Estienne d'Orves F-75009 Paris (FR)
Priority Data:
11 00553 24.02.2011 FR
Title (EN) ELECTRONIC COMPONENT AND PROCESS FOR FABRICATING AND USING GRAPHENE IN AN ELECTRONIC COMPONENT
(FR) COMPOSANT ÉLECTRONIQUE, PROCÉDÉ DE FABRICATION ET UTILISATION DE GRAPHÈNE DANS UN COMPOSANT ÉLECTRONIQUE
Abstract: front page image
(EN)The electronic component (2) comprises at least two superposed conductive or semiconductor layers (4;10,12;14,16). According to one aspect of the invention, the component comprises at least one graphene layer (8) interposed between the conductive or semiconductor layers (4;10,12;14,16), the conductive or semiconductor layers (4;10,12;14,16) being electronically coupled through the thickness of the or each graphene layer (8). Applications especially include magnetic tunnel junctions or spin valves, memristors, etc.
(FR)Le composant électronique (2) comprend au moins deux couches conductrices ou semi-conductrices (4;10,12;14,16) superposées. Selon un aspect de l'invention, il comprend au moins une couche de graphène (8) interposée entre les couches conductrices ou semi-conductrices (4;10,12;14,16), les couches conductrices ou semi-conductrices (4;10,12;14,16) étant couplées électroniquement au travers de l'épaisseur de la ou chaque couche de graphène (8). Application notamment aux jonctions tunnel magnétiques ou non, aux vannes de spin, aux memristors...
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: French (FR)
Filing Language: French (FR)