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Machine translation
1. (WO2012111586) SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/111586    International Application No.:    PCT/JP2012/053222
Publication Date: 23.08.2012 International Filing Date: 13.02.2012
IPC:
H03K 17/06 (2006.01), G02F 1/133 (2006.01), G09G 3/20 (2006.01), G09G 3/36 (2006.01), H03K 17/687 (2006.01)
Applicants: SHARP KABUSHIKI KAISHA [JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522 (JP) (For All Designated States Except US).
SASAKI, Yasushi; (For US Only).
MURAKAMI, Yuhichiroh; (For US Only).
HACHIDA, Takuya; (For US Only).
YAMAMOTO, Etsuo; (For US Only).
OHKAWA, Hiroyuki; (For US Only)
Inventors: SASAKI, Yasushi; .
MURAKAMI, Yuhichiroh; .
HACHIDA, Takuya; .
YAMAMOTO, Etsuo; .
OHKAWA, Hiroyuki;
Agent: HARAKENZO WORLD PATENT & TRADEMARK; Daiwa Minamimorimachi Building, 2-6, Tenjinbashi 2-chome Kita, Kita-ku, Osaka-shi, Osaka 5300041 (JP)
Priority Data:
2011-033743 18.02.2011 JP
Title (EN) SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS
(FR) DISPOSITIF SEMICONDUCTEUR ET APPAREIL D'AFFICHAGE
(JA) 半導体装置及び表示装置
Abstract: front page image
(EN)A circuit (10) is provided with a transistor (T1), a transistor (T2), and a capacitor (TC1) installed between a node (n1) and a CK terminal. The frequency of a clock signal is higher than the frequency of an output signal (OUT), and the capacitance of the capacitor (TC1) becomes smaller as the electric potential of the node (n1) drops, and becomes greater as the electric potential of the node (n1) rises.
(FR)L'invention concerne un circuit (10) comprenant un transistor (T1), un transistor (T2) et un condensateur (TC1) installés entre un nœud (n1) et une borne CK. La fréquence d'un signal d'horloge est supérieure à la fréquence d'un signal de sortie (OUT) et la capacité du condensateur (TC1) devient plus petite à mesure que le potentiel électrique du nœud (n1) chute et devient plus grande à mesure que le potentiel électrique du nœud (n1) augmente.
(JA) 回路(10)は、トランジスタ(T1)と、トランジスタ(T2)と、ノード(n1)およびCK端子の間に設けられる容量(TC1)とを備える。クロック信号の周波数は、出力信号(OUT)の周波数よりも高く、容量(TC1)は、ノード(n1)の電位の低下に伴って小さくなり、ノード(n1)の電位の上昇に伴って大きくなる。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)