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1. (WO2012111451) METHOD FOR STABILIZING GAIN/DISTORTION CHARACTERISTICS, AND CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/111451    International Application No.:    PCT/JP2012/052436
Publication Date: 23.08.2012 International Filing Date: 27.01.2012
IPC:
H03F 1/32 (2006.01), H03F 3/20 (2006.01), H04B 1/04 (2006.01)
Applicants: NEC Corporation [JP/JP]; 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001 (JP) (For All Designated States Except US).
TAWA, Noriaki [JP/JP]; (JP) (For US Only)
Inventors: TAWA, Noriaki; (JP)
Agent: IKEDA, Noriyasu; Hibiya Daibiru Bldg., 2-2, Uchisaiwaicho 1-chome, Chiyoda-ku, Tokyo 1000011 (JP)
Priority Data:
2011-029274 15.02.2011 JP
Title (EN) METHOD FOR STABILIZING GAIN/DISTORTION CHARACTERISTICS, AND CIRCUIT
(FR) PROCÉDÉ DESTINÉ À STABILISER DES CARACTÉRISTIQUES DE GAIN/DE DISTORSION ET CIRCUIT
(JA) 利得・歪み特性安定化方法および回路
Abstract: front page image
(EN)This circuit for stabilizing gain/distortion characteristics which stabilizes signal gain, as well as distortion characteristics of an output signal, of a high-power amplifier to which a high-frequency signal is supplied intermittently at a predetermined cycle period includes a gate bias control circuit which temporarily reduces the depth of gate bias voltage applied to a gate terminal of a transistor for signal amplification during a period in which the high-frequency signal is not being supplied. As a result, drift conditions of the high-power amplifier are recovered from.
(FR)Ce circuit, destiné à stabiliser des caractéristiques de gain/de distorsion qui stabilise le gain d'un signal, ainsi que des caractéristiques de distorsion d'un signal de sortie, d'un amplificateur à haute puissance auquel est fourni par intermittence un signal à haute fréquence selon une période de cycle prédéterminée, comprend un circuit de commande de polarisation de grille qui réduit de manière temporaire la profondeur de la tension de polarisation de grille appliquée à une borne de grille d'un transistor d'amplification de signal au cours d'une période pendant laquelle le signal à haute fréquence n'est pas fourni. Par conséquent, on se remet des conditions de dérive de l'amplificateur à haute puissance.
(JA) 所定の繰り返し周期で間欠的に高周波信号が供給されるハイパワーアンプの、信号利得と出力信号の歪み特性とを安定化させる利得・歪み特性安定化回路は、信号増幅用トランジスタのゲート端子に印加されるゲートバイアス電圧を、高周波信号が供給されていない期間に、一時的に浅くするゲートバイアス制御回路を含む。それによって、ハイパワーアンプのドリフト状態を回復させている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)