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Machine translation
1. (WO2012108576) EDGE COMBINER, AND FREQUENCY MULTIPLIER AND FREQUENCY MULTIPLICATION METHOD USING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/108576    International Application No.:    PCT/KR2011/002001
Publication Date: 16.08.2012 International Filing Date: 23.03.2011
IPC:
H03K 5/12 (2006.01), H03K 5/156 (2006.01), H03L 7/081 (2006.01)
Applicants: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY [KR/KR]; Yonsei University 134, Sinchon-Dong, Seodaemun-Gu Seoul 120-749 (KR) (For All Designated States Except US).
JUNG, Seong-Ook [KR/KR]; (KR) (For US Only).
RYU, Kyung Ho [KR/KR]; (KR) (For US Only).
JUNG, Dong Hun [KR/KR]; (KR) (For US Only)
Inventors: JUNG, Seong-Ook; (KR).
RYU, Kyung Ho; (KR).
JUNG, Dong Hun; (KR)
Agent: KWON, Hyuk-Soo; 3rd Fl., 827-25, Yeoksam-dong, Kangnam-ku Seoul 135-080 (KR)
Priority Data:
10-2011-0011142 08.02.2011 KR
Title (EN) EDGE COMBINER, AND FREQUENCY MULTIPLIER AND FREQUENCY MULTIPLICATION METHOD USING SAME
(FR) DISPOSITIF DE COMBINAISON DE BORD ET MULTIPLICATEUR DE FRÉQUENCE ET PROCÉDÉ DE MULTIPLICATION DE FRÉQUENCE UTILISANT CEUX-CI
(KO) 에지컴바이너, 이를 이용한 주파수 체배기 및 주파수 체배방법
Abstract: front page image
(EN)The present invention relates to a structure of an edge combiner, and to a frequency multiplier and frequency multiplication method using same. The edge combiner according to one embodiment of the present invention uses an additional control unit including an NMOS pass gate, an inverter, and a blocking PMOS transistor in order to control the turnoff operation of a PMOS transistor of a differential cascade voltage switch logic. Consequently, fast operation becomes possible, thereby improving the performance of a frequency multiplier.
(FR)La présente invention se rapporte à une structure d'un dispositif de combinaison de bord et à un multiplicateur de fréquence et à un procédé de multiplication de fréquence utilisant ceux-ci. Le dispositif de combinaison de bord selon un mode de réalisation de la présente invention utilise une unité de commande supplémentaire qui comprend une porte de passage NMOS, un inverseur et un transistor PMOS de blocage de façon à commander l'opération de blocage d'un transistor PMOS d'une logique de commutation de tension en cascade différentielle. Par conséquent, un fonctionnement rapide devient possible, en améliorant de ce fait les performances d'un multiplicateur de fréquence.
(KO)본 발명은 에지컴바이너의 구조 및 이를 이용한 주파수 체배기, 주파수 체배방법에 관한 것이다. 본 발명의 일실시예에 따른 에지컴바이너는 NMOS 패스게이트, 인버터 및 차단 PMOS 트랜지스터로 구성되는 별도의 제어부를 이용하여 차동 캐스코드 전압 스위치 로직의 PMOS 트랜지스터의 턴오프(turn-off) 동작을 제어함으로써, 고속 동작이 가능하게 하여, 주파수 체배기의 성능을 향상시킬 수 있다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)