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1. WO2012103357 - PROCESS FOR FILLING VIAS IN THE MICROELECTRONICS

Publication Number WO/2012/103357
Publication Date 02.08.2012
International Application No. PCT/US2012/022758
International Filing Date 26.01.2012
IPC
C25D 3/18 2006.1
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
3Electroplating; Baths therefor
02from solutions
12of nickel or cobalt
14from baths containing acetylenic or heterocyclic compounds
18Heterocyclic compounds
C25D 5/18 2006.1
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
5Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
18Electroplating using modulated, pulsed or reversing current
C25D 7/12 2006.1
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
7Electroplating characterised by the article coated
12Semiconductors
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H05K 3/42 2006.1
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
40Forming printed elements for providing electric connections to or between printed circuits
42Plated through-holes
CPC
C25D 3/38
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
3Electroplating: Baths therefor
02from solutions
38of copper
C25D 5/02
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
5Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
02Electroplating of selected surface areas
C25D 5/18
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
5Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
18Electroplating using modulated, pulsed or reversing current
C25D 5/611
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
5Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
60Electroplating characterised by the structure or texture of the layers
605Surface topography of the layers, e.g. rough, dendritic or nodular layers
611Smooth layers
C25D 7/123
CCHEMISTRY; METALLURGY
25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
7Electroplating characterised by the article coated
12Semiconductors
123Semiconductors first coated with a seed layer or a conductive layer
H01L 21/2885
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
283Deposition of conductive or insulating materials for electrodes ; conducting electric current
288from a liquid, e.g. electrolytic deposition
2885using an external electrical current, i.e. electro-deposition
Applicants
  • ENTHONE INC. [US]/[US] (AllExceptUS)
  • RICHARDSON, Thomas, B. [US]/[US] (UsOnly)
  • ABYS, Joseph, A. [US]/[US] (UsOnly)
  • SHAO, Wenbo [CN]/[US] (UsOnly)
  • WANG, Chen [CN]/[US] (UsOnly)
  • PANECCASIO, JR., Vincent [US]/[US] (UsOnly)
  • WANG, Cai [CN]/[US] (UsOnly)
  • LIN, Xuan [US]/[US] (UsOnly)
  • ANTONELLIS, Theodore [US]/[US] (UsOnly)
Inventors
  • RICHARDSON, Thomas, B.
  • ABYS, Joseph, A.
  • SHAO, Wenbo
  • WANG, Chen
  • PANECCASIO, JR., Vincent
  • WANG, Cai
  • LIN, Xuan
  • ANTONELLIS, Theodore
Agents
  • FLEISCHUT, Paul, I.J.
Priority Data
61/436,56926.01.2011US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) PROCESS FOR FILLING VIAS IN THE MICROELECTRONICS
(FR) PROCÉDÉ PERMETTANT DE COMBLER DES TROUS D'INTERCONNEXION EN MICROÉLECTRONIQUE
Abstract
(EN) A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
(FR) La présente invention se rapporte à un procédé de métallisation d'un élément de trou interconnexion traversant le silicium dans un dispositif à circuit intégré semi-conducteur. Ledit procédé comprend les étapes consistant à inverser, pendant le cycle de remplissage, la polarité du circuit pendant un intervalle de temps afin de générer un potentiel anodique au niveau dudit substrat de métallisation et de désorber le dispositif d'étalage de la surface de cuivre dans le trou d'interconnexion, suivi par la poursuite du dépôt de cuivre par rétablissement de la surface de cuivre dans le trou d'interconnexion sous la forme d'une cathode dans le circuit, ce qui permet de produire un élément de trou d'interconnexion rempli de cuivre.
Latest bibliographic data on file with the International Bureau