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1. (WO2012102281) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/102281    International Application No.:    PCT/JP2012/051484
Publication Date: 02.08.2012 International Filing Date: 18.01.2012
IPC:
H01L 29/786 (2006.01), H01L 21/8234 (2006.01), H01L 21/8238 (2006.01), H01L 27/08 (2006.01), H01L 27/088 (2006.01), H01L 27/092 (2006.01)
Applicants: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 398, Hase, Atsugi-shi, Kanagawa 2430036 (JP) (For All Designated States Except US).
FUJITA, Masashi [JP/JP]; (JP) (For US Only).
SHIONOIRI, Yutaka; (For US Only).
TOMATSU, Hiroyuki; (For US Only).
KOBAYASHI, Hidetomo; (For US Only)
Inventors: FUJITA, Masashi; (JP).
SHIONOIRI, Yutaka; .
TOMATSU, Hiroyuki; .
KOBAYASHI, Hidetomo;
Priority Data:
2011-015871 28.01.2011 JP
2011-108880 14.05.2011 JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS
Abstract: front page image
(EN)A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.
(FR)La présente invention concerne un premier transistor à effet de champ disposé sur un substrat, comprenant une région isolante disposée sur une première région semi-conductrice, et une seconde région semi-conductrice est disposée sur la région isolante. Une couche isolante est disposée sur le substrat. L'invention concerne également un second transistor à effet de champ disposé sur une surface plate de la couche isolante, et comprenant une couche semi-conductrice oxyde. L'invention concerne enfin une borne de commande. La borne de commande est formée en même temps qu'une source et qu'un drain du second transistor à effet de champ. Une tension servant à commander une tension de seuil du premier transistor à effet de champ est envoyée vers la borne de commande.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)