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Machine translation
1. (WO2012101920) CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/101920    International Application No.:    PCT/JP2011/078930
Publication Date: 02.08.2012 International Filing Date: 14.12.2011
IPC:
H01L 23/28 (2006.01), H01L 21/56 (2006.01), H05K 9/00 (2006.01)
Applicants: MURATA MANUFACTURING CO., LTD. [JP/JP]; 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555 (JP) (For All Designated States Except US).
KAWANO Koji [JP/JP]; (JP) (For US Only)
Inventors: KAWANO Koji; (JP)
Agent: MORISHITA Takekazu; Hommachi Eiwa Building, 2-10, Minamihommachi 4-chome, Chuo-ku, Osaka-shi, Osaka 5410054 (JP)
Priority Data:
2011-014890 27.01.2011 JP
Title (EN) CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF
(FR) MODULE DE CIRCUIT ET SON PROCÉDÉ DE FABRICATION
(JA) 回路モジュール及びその製造方法
Abstract: front page image
(EN)Provided are a circuit module having satisfactory isolation characteristics, and a manufacturing method thereof. An electronic component (14) is mounted on a primary face (S1) of a circuit substrate (12). An insulation layer (16) covers the primary face (S1) of the substrate (12) and the electronic component (14). A depression (20) is formed on a primary face (S3) of the insulation layer (16). A shield layer (18) covers the primary face (S3) of the insulation layer (16) and the interior circumference face of the depression (20).
(FR)La présente invention concerne un module de circuit qui présente des caractéristiques d'isolation satisfaisantes, ainsi que son procédé de fabrication. Un composant électronique (14) est monté sur une face principale (S1) d'un substrat de circuit (12). Une couche d'isolation (16) recouvre la face principale (S1) du substrat (12) et le composant électronique (14). Un creux (20) est formé sur une face principale (S3) de la couche d'isolation (16). Une couche de protection (18) recouvre la face principale (S3) de la couche d'isolation (16) et la face circonférentielle inférieure du creux (20).
(JA) 良好なアイソレーション特性を有する回路モジュール及びその製造方法を提供することである。 電子部品(14)は、回路基板(12)の主面(S1)上に実装されている。絶縁体層(16)は、回路基板(12)の主面(S1)及び電子部品(14)を覆っている。絶縁体層(16)の主面(S3)には溝(20)が設けられている。シールド層(18)は、絶縁体層(16)の主面(S3)及び溝(20)の内周面を覆っている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)