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Machine translation
1. (WO2012100463) METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/100463    International Application No.:    PCT/CN2011/072961
Publication Date: 02.08.2012 International Filing Date: 18.04.2011
IPC:
H01L 21/8232 (2006.01)
Applicants: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN/CN]; No.3 Beitucheng West Road Chaoyang District, Beijing 100029 (CN) (For All Designated States Except US).
ZHU, Huilong [US/US]; (US) (For US Only).
YIN, Haizhou [CN/US]; (US) (For US Only).
LUO, Zhijiong [US/US]; (US) (For US Only)
Inventors: ZHU, Huilong; (US).
YIN, Haizhou; (US).
LUO, Zhijiong; (US)
Agent: HANHOW INTELLECTUAL PROPERTY PARTNERS; ZHU, Haibo W1-1111, f/11, Oriental plaza No.1 East Chang An Avenue Dongcheng District, Beijing 100738 (CN)
Priority Data:
201110033687.5 30.01.2011 CN
Title (EN) METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ PERMETTANT DE FORMER UNE STRUCTURE SEMI-CONDUCTRICE
(ZH) 一种形成半导体结构的方法
Abstract: front page image
(EN)A method for forming a semiconductor structure comprises steps: forming a dummy gate (206) on a semiconductor substrate (202); forming source/drain areas (208) and a channel area (214) circling around the side wall (212) of the dummy gate (206); removing the dummy gate (206) to form a gate gap (222); forming a stress material layer (226) inside of the gate gap (222); annealing the semiconductor substrate (202); removing the stress material layer (226) inside of the gate gap (222); and forming a gate electrode (230) in the gate gap (222).
(FR)La présente invention se rapporte à un procédé permettant de former une structure semi-conductrice. Ledit procédé comprend les étapes consistant à : former une grille factice (206) sur un substrat semi-conducteur (202); former des zones de source/drain (208) et une zone de canal (214) entourant la paroi latérale (212) de la grille factice (206); enlever la grille factice (206) afin de former un espace de grille (222); former une couche de matériau de contrainte (226) à l'intérieur de l'espace de grille (222); recuire le substrat semi-conducteur (202); enlever la couche de matériau de contrainte (226) se trouvant à l'intérieur de l'espace de grille (222); et former une électrode grille (230) dans l'espace de grille (222).
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)