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1. (WO2012097564) A MANUFACTURING METHOD OF SELF-ALIGNED FILM TRANSISTOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/097564    International Application No.:    PCT/CN2011/075653
Publication Date: 26.07.2012 International Filing Date: 13.06.2011
IPC:
H01L 21/336 (2006.01)
Applicants: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL [CN/CN]; Shenzhen Graduate School of Peking University Shenzhen University Town, Xili, Nanshan District Shenzhen, Guangdong 518055 (CN) (For All Designated States Except US).
ZHANG, Shengdong [CN/CN]; (CN) (For US Only).
HE, Xin [CN/CN]; (CN) (For US Only).
WANG, Yi [CN/CN]; (CN) (For US Only).
HAN, Dedong [CN/CN]; (CN) (For US Only).
HAN, Ruqi [CN/CN]; (CN) (For US Only)
Inventors: ZHANG, Shengdong; (CN).
HE, Xin; (CN).
WANG, Yi; (CN).
HAN, Dedong; (CN).
HAN, Ruqi; (CN)
Agent: DHC LAW OFFICE; Suite 2201, Modern International Commercial Building Cross of Fuhua Road and Jintian Road, Futian District Shenzhen, Guangdong 518048 (CN)
Priority Data:
201110020672.5 18.01.2011 CN
Title (EN) A MANUFACTURING METHOD OF SELF-ALIGNED FILM TRANSISTOR
(FR) PROCÉDÉ DE FABRICATION D'UN TRANSISTOR À COUCHES AUTOALIGNÉES
(ZH) 一种自对准薄膜晶体管的制作方法
Abstract: front page image
(EN)A manufacturing method of self-aligned metal oxide film transistor includes that: an active layer having high current carrier concentration is formed; the channel region (5) is self- aligned with gate electrode (2), a channel region (5) is oxidized by plasma having oxidation function; the source and drain region have high carrier concentration; the channel region (5) has low carrier concentration, the transistor has self-aligned structure at the same time. The threshold voltage of transistor is controlled by plasma having oxidation function at the low temperature, so that the controllability of transistor characteristic is increased, the manufacturing process flow is simplified.
(FR)L'invention concerne un procédé de fabrication d'un transistor à couches autoalignées à oxyde de métal comprenant les étapes consistant à : former une couche active ayant une haute concentration en porteurs de courant; autoaligner la région de canal (5) avec une électrode de grille (2), oxyder une région de canal (5) par un plasma ayant une fonction d'oxydation; les régions de source et de drain ont une haute concentration en porteurs de courant, la région de canal (5) a une faible concentration en porteurs de courant, et le transistor a une structure autoalignée. La tension seuil du transistor est commandée par un plasma ayant une fonction d'oxydation à basse température, si bien que l'aptitude à la commande des caractéristiques du transistor est augmentée, et le flux du processus de fabrication est simplifié.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)