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Machine translation
1. (WO2012096066) POWER SEMICONDUCTOR MODULE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/096066    International Application No.:    PCT/JP2011/077747
Publication Date: 19.07.2012 International Filing Date: 01.12.2011
IPC:
H01L 25/07 (2006.01), H01L 25/18 (2006.01), H02M 7/48 (2007.01)
Applicants: CALSONIC KANSEI CORPORATION [JP/JP]; 2-1917 Nisshin-cho, Kita-ku, Saitama-shi, Saitama 3318501 (JP) (For All Designated States Except US).
SATOU Yutaka [JP/JP]; (JP) (For US Only).
YASUDA Hiroki [JP/JP]; (JP) (For US Only).
KOUI Kenichi [JP/JP]; (JP) (For US Only)
Inventors: SATOU Yutaka; (JP).
YASUDA Hiroki; (JP).
KOUI Kenichi; (JP)
Agent: AYATA Masamichi; 203 Royal-Chateau-Kawasaki, 22-2 Omiya-cho, Saiwai-ku, Kawasaki-shi, Kanagawa 2120014 (JP)
Priority Data:
2011-002629 11.01.2011 JP
Title (EN) POWER SEMICONDUCTOR MODULE
(FR) MODULE SEMICONDUCTEUR DE PUISSANCE
(JA) パワー半導体モジュール
Abstract: front page image
(EN)A power semiconductor module (1) has a lower IGBT chip (4) and an upper IGBT chip (5) disposed between an upper ceramic wiring substrate (3) and a lower ceramic wiring substrate (2). A P lead terminal (10), N lead terminal (11), and OUT lead terminal (12) that electrically connect the lower IGBT chip (4) and the upper IGBT chip (5) to the outside are mounted between the upper ceramic wiring substrate (3) and the lower ceramic wiring substrate (2).
(FR)Module semiconducteur (1) de puissance doté d'une puce IGBT inférieure (4) et d'une puce IGBT supérieure (5) disposées entre un substrat céramique supérieur (3) de câblage et un substrat céramique inférieur (2) de câblage. Une borne (10) de connexion P, une borne (11) de connexion N, et une borne (12) de connexion OUT qui relient électriquement la puce IGBT inférieure (4) et la puce IGBT supérieure (5) à l'extérieur sont montées entre le substrat céramique supérieur (3) de câblage et le substrat céramique inférieur (2) de câblage.
(JA) 上側セラミック配線基板3と下側セラミック配線基板2との間にロアIGBTチップ4およびアッパIGBTチップ5を配置したパワー半導体モジュール1において、ロアIGBTチップ4およびアッパIGBTチップ5と外部とを電気的に接続するPリード端子10、Nリード端子11およびOUTリード端子12を、上側セラミック配線基板3と下側セラミック配線基板2との間に介装した。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)