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1. (WO2012093544) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2012/093544 International Application No.: PCT/JP2011/078278
Publication Date: 12.07.2012 International Filing Date: 07.12.2011
IPC:
H01L 29/78 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/316 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/12 (2006.01) ,H01L 29/739 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314
Inorganic layers
316
composed of oxides or glassy oxides or oxide-based glass
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
Applicants: HIYOSHI, Toru[JP/JP]; JP (UsOnly)
MASUDA, Takeyoshi[JP/JP]; JP (UsOnly)
SUMITOMO ELECTRIC INDUSTRIES, LTD.[JP/JP]; 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP (AllExceptUS)
Inventors: HIYOSHI, Toru; JP
MASUDA, Takeyoshi; JP
Agent: Fukami Patent Office, p.c.; Nakanoshima Central Tower, 2-7, Nakanoshima 2-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
2011-00120506.01.2011JP
Title (EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置の製造方法
Abstract:
(EN) This method for manufacturing a MOSFET (100) comprises a step for preparing a silicon carbide substrate (1), a step for forming an active layer (7) on the silicon carbide substrate (1), a step for forming a gate oxide film (91) on the active layer (7), a step for forming a gate electrode (93) on the gate oxide film (91), a step for forming a source contact electrode (92) on the active layer (7), and a step for forming a source wiring (95) on the source contact electrode (92). The step for forming the source wiring (95) includes a step for forming an electroconductive film on the source contact electrode (92) and a step for processing the electroconductive film by etching the electroconductive film using reactive ion etching. The method for manufacturing the MOSFET (100) further comprises an annealing step in which the silicon carbide substrate (1) is heated to a temperature of 50°C or higher after the step for processing the electroconductive film.
(FR) Le présent procédé de fabrication d'un MOSFET (100) comprend une étape consistant à préparer un substrat de carbure de silicium (1), une étape consistant à former une couche active (7) sur le substrat de carbure de silicium (1), une étape consistant à former une pellicule d'oxyde de gâchette (91) sur la couche active (7), une étape consistant à former une électrode de gâchette (93) sur la pellicule d'oxyde de gâchette (91), une étape consistant à former une électrode de contact de source (92) sur la couche active (7), et une étape consistant à former un circuit de source (95) sur l'électrode de contact de source (92). L'étape consistant à former le circuit de source (95) comprend une étape consistant à former une pellicule électroconductrice sur l'électrode de contact de source (92) et une étape consistant à traiter la pellicule électroconductrice en gravant la pellicule électroconductrice par gravure ionique réactive. Le procédé de fabrication du MOSFET (100) comprend en outre une étape de recuit dans laquelle le substrat de carbure de silicium (1) est chauffé à une température supérieure ou égale à 50 °C après l'étape consistant à traiter la pellicule électroconductrice.
(JA)  MOSFET(100)の製造方法は、炭化珪素基板(1)を準備する工程と、炭化珪素基板(1)上に活性層(7)を形成する工程と、活性層(7)上にゲート酸化膜(91)を形成する工程と、ゲート酸化膜(91)上にゲート電極(93)を形成する工程と、活性層(7)上にソースコンタクト電極(92)を形成する工程と、ソースコンタクト電極(92)上にソース配線(95)を形成する工程とを備える。ソース配線(95)を形成する工程は、ソースコンタクト電極(92)上に導電体膜を形成する工程と、導電体膜を反応性イオンエッチングによりエッチングすることにより導電体膜を加工する工程とを含む。そして、MOSFET100の製造方法は、導電体膜を加工する工程よりも後に、炭化珪素基板(1)を50℃以上の温度に加熱するアニールを実施する工程をさらに備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)