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1. WO2012086871 - SEMICONDUCTOR CHIP STACK PACKAGE AND MANUFACTURING METHOD THEREOF

Publication Number WO/2012/086871
Publication Date 28.06.2012
International Application No. PCT/KR2011/001166
International Filing Date 22.02.2011
IPC
H01L 23/10 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
02Containers; Seals
10characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
CPC
H01L 21/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/26145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
2612Auxiliary members for layer connectors, e.g. spacers
26122being formed on the semiconductor or solid-state body to be connected
26145Flow barriers
H01L 2224/27013
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
27Manufacturing methods
27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
27013for holding or confining the layer connector, e.g. solder flow barrier
H01L 2224/29139
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
291with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
29138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
29139Silver [Ag] as principal constituent
H01L 2224/2919
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
2919with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
Applicants
  • KOREA INSTITUTE OF MACHINERY & MATERIALS [KR]/[KR] (AllExceptUS)
  • LEE, Jae-Hak [KR]/[KR] (UsOnly)
  • LEE, Chang-Woo [KR]/[KR] (UsOnly)
  • SONG, Joon-Yub [KR]/[KR] (UsOnly)
  • HA, Tae-Ho [KR]/[KR] (UsOnly)
Inventors
  • LEE, Jae-Hak
  • LEE, Chang-Woo
  • SONG, Joon-Yub
  • HA, Tae-Ho
Agents
  • PANKOREA PATENT AND LAW FIRM
Priority Data
10-2010-013193921.12.2010KR
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR CHIP STACK PACKAGE AND MANUFACTURING METHOD THEREOF
(FR) BOÎTIER D'EMPILEMENT DE PUCES À SEMI-CONDUCTEURS ET SON PROCÉDÉ DE FABRICATION
Abstract
(EN)
The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity.
(FR)
La présente invention porte sur un boîtier d'empilement de puces à semi-conducteurs et sur son procédé de fabrication, et, plus particulièrement, sur un boîtier d'empilement de puces à semi-conducteurs et sur son procédé de fabrication, dans lesquels une pluralité de puces peuvent être disposées et fixées rapidement sans un dispositif ou une opération précis, de façon à améliorer la productivité.
Also published as
Latest bibliographic data on file with the International Bureau