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1. WO2012082416 - CPU IN MEMORY CACHE ARCHITECTURE

Publication Number WO/2012/082416
Publication Date 21.06.2012
International Application No. PCT/US2011/063204
International Filing Date 04.12.2011
IPC
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 13/14 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
CPC
G06F 12/0842
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0842for multiprocessing or multitasking
G06F 15/7821
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
7821Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants
  • FISH, Russell, Hamilton [US]/[US]
Inventors
  • FISH, Russell, Hamilton
Agents
  • MELITO, Carl Frank
Priority Data
12/965,88512.12.2010US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CPU IN MEMORY CACHE ARCHITECTURE
(FR) ARCHITECTURE DE CACHE À CPU EN MÉMOIRE
Abstract
(EN)
One exemplary CPU in memory cache architecture embodiment comprises a demultiplexer, and multiple partitioned caches for each processor, said caches comprising an I-cache dedicated to an instruction addressing register and an X-cache dedicated to a source addressing register; wherein each processor accesses an on-chip bus containing one RAM row for an associated cache; wherein all caches are operable to be filled or flushed in one RAS cycle, and all sense amps of the RAM row can be deselected by the demultiplexer to a duplicate corresponding bit of its associated cache. Several methods are also disclosed which evolved out of, and help enhance, the various embodiments. It is emphasized that this abstract is provided to enable a searcher to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
(FR)
Selon l'invention, un mode de réalisation d'architecture de cache à CPU en mémoire illustratif de l'invention comprend un démultiplexeur, et de multiples caches partitionnés pour chaque processeur, lesdits caches comprenant un cache I dédié à un registre d'adressage d'instruction et un cache X dédié à un registre d'adressage de source ; chaque processeur accédant à un bus sur puce contenant une rangée de RAM pour un cache associé ; tous les caches étant utilisables pour être remplis ou vidés en un seul cycle RAS, et tous les amplificateurs de lecture de la rangée de RAM pouvant être désélectionnés par le démultiplexeur vers un bit correspondant dupliqué de leur cache associé. Plusieurs procédés sont également décrits qui ont été élaborés à partir des divers modes de réalisation et aident à les améliorer. On attirera l'attention sur le fait que cet abrégé est fourni pour permettre à un chercheur d'identifier rapidement l'objet de la description technique et est soumis en comprenant qu'il ne sera pas utilisé pour interpréter ou limiter la portée ou la signification des revendications.
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