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1. WO2012068762 - IC CHIP PACKAGE OF SIP SYSTEM INTEGRATION LEVEL AND MANUFACTURING METHOD THEREOF

Publication Number WO/2012/068762
Publication Date 31.05.2012
International Application No. PCT/CN2010/080520
International Filing Date 30.12.2010
IPC
H01L 25/16 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
H01L 23/488 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
H01L 21/50 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
CPC
H01L 21/565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
H01L 2223/5442
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
5442comprising non digital, non alphanumeric information, e.g. symbols
H01L 2223/54486
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
54473for use after dicing
54486Located on package parts, e.g. encapsulation, leads, package substrate
H01L 2224/2919
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
2919with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
Applicants
  • 天水华天科技股份有限公司 TIANSHUI HUATIAN TECHNOLOGY CO., LTD. [CN]/[CN] (AllExceptUS)
  • 谢建友 XIE, Jianyou [CN]/[CN] (UsOnly)
  • 李习周 LI, Xizhou [CN]/[CN] (UsOnly)
  • 慕蔚 MU, Wei [CN]/[CN] (UsOnly)
  • 王永忠 WANG, Yongzhong [CN]/[CN] (UsOnly)
  • 魏海东 WEI, Haidong [CN]/[CN] (UsOnly)
Inventors
  • 谢建友 XIE, Jianyou
  • 李习周 LI, Xizhou
  • 慕蔚 MU, Wei
  • 王永忠 WANG, Yongzhong
  • 魏海东 WEI, Haidong
Agents
  • 甘肃省知识产权事务中心 GANSU PROVINCE INTELLECTUAL PROPERTY RIGHTS BUSINESS CENTER
Priority Data
201010561304.726.11.2010CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) IC CHIP PACKAGE OF SIP SYSTEM INTEGRATION LEVEL AND MANUFACTURING METHOD THEREOF
(FR) BOÎTIER DE PUCE DE CIRCUIT INTÉGRÉ (IC) D'UN NIVEAU D'INTÉGRATION DE SYSTÈME SIP ET PROCÉDÉ DE PRODUCTION CORRESPONDANT
(ZH) SIP系统集成级IC芯片封装件及其制作方法
Abstract
(EN)
An IC chip package of an SIP system integration level and a manufacturing method thereof are provided. The package includes a substrate (1), passive components (8,9,10,11) and two IC chips (3,5) arranged on the substrate, adhesive films (2,4) arranged between the two IC chips and the substrate, wherein the IC chips are connected to the first pads (6) on the substrate by bonding wires (7), and a molding encapsulant (13) is coated on the substrate. The chips are attached on the substrate, after processes of flow back soldering, washing, chips mounting, plasma washing, press-soldering, printing, cutting and packaging, the IC chip package of the SIP system integration level is achieved.
(FR)
L'invention concerne un boîtier de puce de circuit intégré (IC) d'un niveau d'intégration de système SIP et un procédé de production correspondant. Le boîtier comprend un substrat (1), des composants passifs (8,9,10,11) et deux puces de circuit intégré (3,5) qui sont disposées sur le substrat, des films adhésifs (2,4) qui sont disposés entre les deux puces de circuit intégré (IC) et le substrat, lesdites puces de circuit intégré (IC) étant reliées aux premières pastilles (6) sur le substrat par des fils de connexion (7), et un agent d'encapsulation de moulage (13) est appliqué sur le substrat. Lesdites puces sont fixées sur le substrat, après des processus de soudage par refusion, lavage, montage de puces, lavage au plasma, soudage par pression, impression, découpe, encapsulation, l'on obtient le boîtier de puce de circuit intégré (IC) du niveau d'intégration de système SIP.
Also published as
Latest bibliographic data on file with the International Bureau