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1. WO2012068486 - LOAD/STORE CIRCUITRY FOR A PROCESSING CLUSTER

Publication Number WO/2012/068486
Publication Date 24.05.2012
International Application No. PCT/US2011/061444
International Filing Date 18.11.2011
IPC
G06F 13/14 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
CPC
G06F 15/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 15/80
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 15/8053
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
8053Vector processors
G06F 8/40
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
8Arrangements for software engineering
40Transformation of program code
G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/30054
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3005to perform operations for flow control
30054Unconditional branch instructions
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US] (AllExceptUS)
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
  • JOHNSON, William [US]/[US] (UsOnly)
  • GLOTZBACH, John W. [US]/[US] (UsOnly)
  • SHEIKH, Hamid [PK]/[US] (UsOnly)
  • JAYARAJ, Ajay [IN]/[US] (UsOnly)
  • BUSCH, Stephen [DE]/[FR] (UsOnly)
  • CHINNAKONDA, Murali [US]/[US] (UsOnly)
  • NYE, Jeffrey L. [US]/[US] (UsOnly)
  • NAGATA, Toshio [JP]/[US] (UsOnly)
  • GUPTA, Shalini [IN]/[US] (UsOnly)
  • NYCHKA, Robert J. [CA]/[US] (UsOnly)
  • BARTLEY, David H. [US]/[US] (UsOnly)
  • SUNDARARAJAN, Ganesh [CA]/[US] (UsOnly)
Inventors
  • JOHNSON, William
  • GLOTZBACH, John W.
  • SHEIKH, Hamid
  • JAYARAJ, Ajay
  • BUSCH, Stephen
  • CHINNAKONDA, Murali
  • NYE, Jeffrey L.
  • NAGATA, Toshio
  • GUPTA, Shalini
  • NYCHKA, Robert J.
  • BARTLEY, David H.
  • SUNDARARAJAN, Ganesh
Agents
  • FRANZ, Warren L.
Priority Data
13/232,77414.09.2011US
61/415,20518.11.2010US
61/415,21018.11.2010US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LOAD/STORE CIRCUITRY FOR A PROCESSING CLUSTER
(FR) CIRCUIT DE CHARGEMENT/ENREGISTREMENT POUR GRAPPE DE TRAITEMENT
Abstract
(EN)
An apparatus for performing parallel processing is provided. The apparatus has a message bus (1420), a data bus (1422), and a load/store unit (1408). The load/store unit (1408) has a system interface (5416), a data interface (5420), a message interface (5418), an instruction memory (5405), a data memory (5403), a buffer (5406), thread-scheduling circuitry (5401, 5404), and a processor (5402). The system interface (5416) is configured to communicate with system memory (1416). The data interface (5420) is coupled to the data bus (1422). The message interface (5418) is coupled to the message bus (1420). The buffer (5406) is coupled to the data interface (5420). The thread-scheduling circuitry (5401, 5404) is coupled to the message interface (5418), and the processor (5402) is coupled to the data memory (5403), the buffer (5406), the instruction memory (5405), thread-scheduling circuitry (5401, 5404), and the system interface (5416).
(FR)
La présente invention concerne un appareil pour réaliser un traitement en parallèle. L'appareil présente un bus de messages (1420), un bus de données (1422) et une unité de chargement/enregistrement (1408). L'unité de chargement/enregistrement (1408) présente une interface système (5416), une interface de données (5420), une interface de messages (5418), une mémoire d'instructions (5405), une mémoire de données (5403), un tampon (5406), un circuit de programmation de fil d'exécution (5401, 5404) et un processeur (5402). L'interface système (5416) est conçue pour communiquer avec la mémoire système (1416). L'interface de données (5420) est couplée au bus de données (1422). L'interface de messages (5418) est couplée au bus de messages (1420). Le tampon (5406) est couplé à l'interface de données (5420). Le circuit de programmation de fil d'exécution (5401, 5404) est couplé à l'interface de messages (5418), et le processeur (5402) est couplé à la mémoire de données (5403), au tampon (5406), à la mémoire d'instructions (5405), au circuit de programmation de fil d'exécution (5401, 5404), et à l'interface système (5416).
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