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1. WO2012066697 - PROGRAMMABLE LOGIC DEVICE

Publication Number WO/2012/066697
Publication Date 24.05.2012
International Application No. PCT/JP2011/002893
International Filing Date 24.05.2011
IPC
G09C 1/00 2006.01
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
CCIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
1Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
H04L 9/06 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Arrangements for secret or secure communication
06the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/10 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Arrangements for secret or secure communication
10with particular housing, physical features or manual controls
CPC
H04L 2209/125
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
2209Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
12Details relating to cryptographic hardware or logic circuitry
125Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
H04L 9/0625
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Cryptographic mechanisms or cryptographic; arrangements for secret or secure communication
06the encryption apparatus using shift registers or memories for block-wise ; or stream; coding, e.g. DES systems ; or RC4; Hash functions; Pseudorandom sequence generators
0618Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
0625with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
H04L 9/0631
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Cryptographic mechanisms or cryptographic; arrangements for secret or secure communication
06the encryption apparatus using shift registers or memories for block-wise ; or stream; coding, e.g. DES systems ; or RC4; Hash functions; Pseudorandom sequence generators
0618Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
0631Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Applicants
  • パナソニック株式会社 PANASONIC CORPORATION [JP]/[JP] (AllExceptUS)
  • 森敦弘 MORI, Atsuhiro (UsOnly)
Inventors
  • 森敦弘 MORI, Atsuhiro
Agents
  • 前田弘 MAEDA, Hiroshi
Priority Data
2010-25784518.11.2010JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) PROGRAMMABLE LOGIC DEVICE
(FR) DISPOSITIF À LOGIQUE PROGRAMMABLE
(JA) プログラマブル・ロジック・デバイス
Abstract
(EN)
In addition to a plurality of operating element groups (103) formed by arranging each of a plurality of operating elements (102), a programmable logic device (101) contains a plurality of first sorting cells (104) which are capable of a per cycle function change by each such cell being set by an external source, and which are also capable of sorting a 64-bit input signal in an arbitrary order and outputting a 64-bit signal. Operations other than arithmetic logic operations, i.e., processing of data sorting, appropriate bit positioning, etc., are executed with the first sorting cells (104).
(FR)
Outre une pluralité de groupes d'éléments fonctionnels (103) créés par l'agencement de chaque élément fonctionnel d'une pluralité d'éléments fonctionnels (102), un dispositif à logique programmable (101) contient une pluralité de cellules de premier tri (104) qui peuvent changer de fonction à chaque cycle, ce qui permet que le paramétrage de chacune de ces cellules soit effectué par une source externe, et ces cellules peuvent aussi trier un signal d'entrée de 64 bits dans un ordre arbitraire et émettre un signal de 64 bits. Les opérations qui ne sont pas des opérations arithmétiques et logiques, c'est-à-dire la réalisation du tri de données, le positionnement correct des bits, etc. sont exécutées à l'aide desdites cellules de premier tri (104).
(JA)
 プログラマブル・ロジック・デバイス(101)は、各々複数の演算エレメント(102)を配置してなる複数の演算エレメント群(103)に加えて、各々外部からの設定によって毎サイクル機能変更が可能であり、かつ64ビットの入力信号を任意の順番に並べ替えて64ビット信号を出力することが可能な第1の並べ替えセル(104)を複数内蔵する。算術論理演算以外の演算であるデータの並べ替えや適切なビット配置等の処理は、第1の並べ替えセル(104)で実行する。
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