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1. WO2012063329 - SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Publication Number WO/2012/063329
Publication Date 18.05.2012
International Application No. PCT/JP2010/070002
International Filing Date 10.11.2010
IPC
H01L 21/338 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
338with a Schottky gate
H01L 29/778 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
778with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/812 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
80with field effect produced by a PN or other rectifying junction gate
812with a Schottky gate
CPC
H01L 21/0254
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02518Deposited layers
02521Materials
02538Group 13/15 materials
0254Nitrides
H01L 29/0607
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
H01L 29/0657
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0657characterised by the shape of the body
H01L 29/2003
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
12characterised by the materials of which they are formed
20including, apart from doping materials or other impurities, only AIIIBV compounds
2003Nitride compounds
H01L 29/205
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
12characterised by the materials of which they are formed
20including, apart from doping materials or other impurities, only AIIIBV compounds
201including two or more compounds ; , e.g. alloys
205in different semiconductor regions ; , e.g. heterojunctions
H01L 29/7786
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
778with two-dimensional charge carrier gas channel, e.g. HEMT ; ; with two-dimensional charge-carrier layer formed at a heterojunction interface
7786with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Applicants
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP] (AllExceptUS)
  • 大石 敏之 OISHI, Toshiyuki (UsOnly)
  • 大塚 浩志 OTSUKA, Hiroshi (UsOnly)
  • 山中 宏治 YAMANAKA, Koji (UsOnly)
  • 山内 和久 YAMAUCHI, Kazuhisa (UsOnly)
  • 半谷 政毅 HANGAI, Masatake (UsOnly)
  • 中山 正敏 NAKAYAMA, Masatoshi (UsOnly)
Inventors
  • 大石 敏之 OISHI, Toshiyuki
  • 大塚 浩志 OTSUKA, Hiroshi
  • 山中 宏治 YAMANAKA, Koji
  • 山内 和久 YAMAUCHI, Kazuhisa
  • 半谷 政毅 HANGAI, Masatake
  • 中山 正敏 NAKAYAMA, Masatoshi
Agents
  • 曾我 道治 SOGA, Michiharu
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE PRODUCTION D'UN DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置、および半導体装置の製造方法
Abstract
(EN)
The problem addressed by the present invention is to achieve both increased gain and increased bandwidth (in other words, achieving both a reduction in gate-drain capacitance and a reduction in source-drain capacitance). The present invention is provided with: a GaN channel layer (3) through which electrons travel; a barrier layer (4) that contains N and at least one of In, Al, and Ga and that is provided over the GaN channel layer in order to form a two-dimensional electron gas in the GaN channel layer; and a gate electrode (8), a source electrode (6), and a drain electrode (7). The present invention is further provided with a plate (20) that is between the gate electrode (8) and the drain electrode (7), is provided in a manner so as to contact a portion of the barrier layer (4), and is formed from a polarized material.
(FR)
La présente invention a pour but d'obtenir une augmentation de gain et de largeur de bande (en d'autres termes, obtenir à la fois une réduction de la capacitance grille-drain et une réduction de la capacitance source-drain). La présente invention est pourvue de : une couche de canal GaN (3) à travers laquelle circulent des électrons ; une couche barrière (4) qui contient N et au moins un élément parmi In, Al et Ga et qui est disposée sur la couche de canal GaN afin de former un gaz électronique bidimensionnel dans la couche de canal GaN ; et une électrode grille (8), une électrode source (6), et une électrode drain (7). La présente invention est en outre pourvue d'une plaque (20) qui se situe entre l'électrode grille (8) et l'électrode drain (7), qui est disposée de manière à entrer en contact avec une partie de la couche barrière (4), et est formée à partir d'un matériau polarisé.
(JA)
 高利得化と広帯域化を両立(すなわち、ゲート・ドレイン間容量の低減と、ソース・ドレイン間容量の低減を両立)することを課題とする。電子が走行するGaNチャネル層(3)と、GaNチャネル層に2次元電子ガスを形成するために、GaNチャネル層の上部に設けられたIn、Al、Gaのいずれか1つ以上とNを含むバリア層(4)と、ゲート電極(8)、ソース電極(6)、およびドレイン電極(7)とを備え、ゲート電極(8)とドレイン電極(7)との間であり、かつバリア層(4)の一部と接するように設けられた、分極を持った材料によるプレート(20)をさらに備える。
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