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1. WO2012062175 - METHOD FOR MANUFACTURING DOUBLE-GATE STRUCTURES

Publication Number WO/2012/062175
Publication Date 18.05.2012
International Application No. PCT/CN2011/081718
International Filing Date 03.11.2011
IPC
H01L 21/70 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
H01L 21/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
CPC
H01L 21/28518
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
283Deposition of conductive or insulating materials for electrodes ; conducting electric current
285from a gas or vapour, e.g. condensation
28506of conductive layers
28512on semiconductor bodies comprising elements of Group IV of the Periodic System
28518the conductive layers comprising silicides
H01L 21/823443
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
823437with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
823443silicided or salicided gate conductors
H01L 21/823468
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
823468with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
H01L 29/66484
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66484with multiple gate, at least one gate being an insulated gate
Applicants
  • CSMC TECHNOLOGIES FAB1 CO., LTD [CN]/[CN] (AllExceptUS)
  • CSMC TECHNOLOGIES FAB2 CO., LTD. [CN]/[CN] (AllExceptUS)
  • WANG, Le [CN]/[CN] (UsOnly)
Inventors
  • WANG, Le
Agents
  • ADVANCE CHINA I.P. LAW OFFICE
Priority Data
201010538334.609.11.2010CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR MANUFACTURING DOUBLE-GATE STRUCTURES
(FR) PROCÉDÉ DE FABRICATION DE STRUCTURES À DOUBLE GRILLE
Abstract
(EN)
A method for manufacturing a double-gate structure is provided. The method includes providing a substrate; forming a first gate region (201) on a surface of the substrate using a first gate layer; forming a second gate layer which covers the first gate layer on the surface of the substrate; forming an etch-stop layer (203) on the second gate layer; forming a silicide layer (205) on the etch-stop layer (203); and forming a second gate region, different from the first gate region (201), containing the second gate layer and the silicide layer (205) without the etch-stop layer (203). The etch-stop layer (203) is arranged between the second gate layer and the silicide layer (205) to facilitate even etching of the second gate layer around the first gate region (201).
(FR)
Cette invention concerne un procédé de fabrication d'une structure à double grille. Ledit procédé comprend les étapes consistant à : utiliser un substrat; former une première région de grille (201) sur une surface du substrat au moyen d'une première couche de grille; former une seconde de grille qui recouvre la première couche de grille sur la surface du substrat; former une couche d'arrêt de gravure (203) sur la seconde couche de grille; former une couche de siliciure (205) sur al couche d'arrêt de gravure (203); et former une seconde région de grille, différente de la première région de grille (201), contenant la seconde couche de grille et la couche de siliciure (205) sans la couche d'arrêt de gravure (203). Ladite couche d'arrêt de gravure (203) est disposée entre la seconde couche de grille et la couche de siliciure (205) de façon à promouvoir la régularité de la gravure de la seconde couche de grille autour de la première région de grille (201).
Also published as
Latest bibliographic data on file with the International Bureau