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1. WO2012062021 - METHOD FOR MANUFACTURING CONTACT HOLES IN CMOS DEVICE BY GATE-LAST PROCESS

Publication Number WO/2012/062021
Publication Date 18.05.2012
International Application No. PCT/CN2011/000261
International Filing Date 21.02.2011
IPC
H01L 21/8238 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8238Complementary field-effect transistors, e.g. CMOS
H01L 23/52 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
H01L 21/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
CPC
H01L 21/823814
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823814with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
H01L 21/823871
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823871interconnection or wiring or contact manufacturing related aspects
H01L 23/485
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
482consisting of lead-in layers inseparably applied to the semiconductor body
485consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 29/495
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
495the conductor material next to the insulator being a simple metal, e.g. W, Mo
H01L 29/4966
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
4966the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
H01L 29/517
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
51Insulating materials associated therewith
517the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Applicants
  • 中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN]/[CN] (AllExceptUS)
  • 闫江 YAN, Jiang [US]/[US] (UsOnly)
Inventors
  • 闫江 YAN, Jiang
Agents
  • 中国专利代理(香港)有限公司 CHINA PATENT AGENT (H. K.) LTD.
Priority Data
201010542475.511.11.2010CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) METHOD FOR MANUFACTURING CONTACT HOLES IN CMOS DEVICE BY GATE-LAST PROCESS
(FR) PROCÉDÉ DE RÉALISATION DE TROUS DE CONTACT DANS UN DISPOSITIF CMOS PAR UN PROCESSUS DE CHARGE DE PORTE
(ZH) 采用后栅工艺制备CMOS器件中接触孔的方法
Abstract
(EN)
A method for manufacturing contact holes in Complementary Metal-Oxide-Semiconductor (CMOS) device by gate-last process includes that: forming a first type Metal-Oxide-Semiconductor (MOS) high K dielectric/metal gate (HKMG); forming and metalizing lower contact holes of source/drain electrodes of the first type MOS and a second type MOS, and at the same time forming the HKMG of the second type MOS, wherein filling the same material in the lower contact holes of source/drain electrodes as the metal gate of the second type MOS; forming and metalizing the contact holes of the metal gates of the first type and the second MOS and upper contact holes of source/drain electrodes of the first type MOS and the second type MOS, wherein the upper contact holes of source/drain electrodes are aligned with the lower contact holes of source/drain electrodes. The difficulty of the contact holes etching and the metal depositing is reduced, the process step is simplified, and the reliability of the device is increased by the method.
(FR)
La présente invention concerne un procédé de réalisation de trous de contact dans un dispositif à semi-conducteur métal-oxyde complémentaire (CMOS) par un processus de charge de porte, consistant : à former une porte (HKMG) métal/diélectrique à K élevé de semi-conducteur métal-oxyde (MOS) d'un premier type; à former et à métalliser des trous de contact inférieurs d'électrodes source/drain du MOS du premier type et d'un MOS d'un second type, et dans le même temps à former le HKMG du MOS de second type, le même matériau étant employé pour remplir les trous de contact inférieurs des électrodes source/drain que la porte métallique du MOS de second type; à former et à métalliser les trous de contact des portes métalliques des MOS de premier et de second type, et des trous de contact supérieurs des électrodes source/drain des MOS de premier type et de second type, les trous de contact supérieurs des électrodes source/drain étant alignées avec les trous de contact inférieurs des électrodes source/drain. Le procédé permet de réduire la difficulté associée à la gravure des trous de contact et au dépôt de métal, de simplifier l'étape de traitement et d'augmenter la fiabilité du dispositif.
Also published as
Latest bibliographic data on file with the International Bureau