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1. WO2012061381 - CRACK ARREST VIAS FOR IC DEVICES

Publication Number WO/2012/061381
Publication Date 10.05.2012
International Application No. PCT/US2011/058779
International Filing Date 01.11.2011
IPC
H01L 23/48 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
CPC
H01L 2224/0235
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0235Shape of the redistribution layers
H01L 2224/02375
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02375Top view
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/05012
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
0501Shape
05012in top view
H01L 2224/05015
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
0501Shape
05012in top view
05015being circular or elliptic
H01L 2224/05552
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US] (AllExceptUS)
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
  • MCCARTHY, Robert, F. [US]/[US] (UsOnly)
  • BEDDINGFIELD, Stanley, C. [US]/[US] (UsOnly)
Inventors
  • MCCARTHY, Robert, F.
  • BEDDINGFIELD, Stanley, C.
Agents
  • FRANZ, Warren, L.
Priority Data
12/917,14401.11.2010US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CRACK ARREST VIAS FOR IC DEVICES
(FR) INTERCONNEXIONS PARE-FISSURE POUR DISPOSITIFS À CI
Abstract
(EN)
An integrated circuit (IC) device (300) includes a substrate (305) having a top surface (304) including active circuitry (309) including a plurality of I/O nodes (308), and a plurality of die pads (302) coupled to the plurality of I/O nodes. A first dielectric layer (306) including first dielectric vias (312) is over the plurality of die pads. A redirect layer (RDL) (314) including a plurality of RDL capture pads (318) is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer (320) including second dielectric vias (322) is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ± 30 degrees from the line. Under bump metallization (UBM) pads (324) are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors (326) are on the UBM pads.
(FR)
L'invention concerne un dispositif (300) à circuit intégré (IC) comprenant un substrat (305) ayant une surface supérieure (304) qui contient des circuits actifs (309) incluant une pluralité de nœuds d'E/S (308), et une pluralité de pastilles de matrice (302) connectées à la pluralité de nœuds d'E/S. Une première couche diélectrique (306) comprenant des premières interconnexions diélectriques (312) se trouve au-dessus de la pluralité de pastilles de matrice. Une couche de redirection (RDL) (314) comprenant une pluralité de pastilles de capture RDL (318) est connectée à la pluralité de pastilles de matrice au-dessus des premières interconnexions diélectriques. Une deuxième couche diélectrique (320) comprenant des deuxièmes interconnexions diélectriques (322) se trouve au-dessus de la pluralité de pastilles de capture RDL. Au moins l'une des deuxièmes interconnexions diélectriques est une interconnexion pare-fissure qui présente une forme d'interconnexion incluant un sommet qui fait face à l'opposé d'un point de contrainte neutre de la matrice de CI et qui est orienté le long d'une ligne depuis le point de contrainte neutre jusqu'à l'interconnexion pare-fissure vers la face dans une plage de ± 30 degrés par rapport à la ligne. Des pastilles à métallisation sous bosse (UBM) (324) sont connectées à la pluralité de pastilles de capture RDL au-dessus des deuxièmes interconnexions diélectriques et des connecteurs de liaison métalliques (326) se trouvent sur les pastilles UBM.
Also published as
Latest bibliographic data on file with the International Bureau