Processing

Please wait...

Settings

Settings

Goto Application

1. WO2012058074 - THERMAL ISOLATION IN 3D CHIP STACKS USING GAP STRUCTURES AND CONTACTLESS COMMUNICATIONS

Publication Number WO/2012/058074
Publication Date 03.05.2012
International Application No. PCT/US2011/056957
International Filing Date 19.10.2011
IPC
H01L 23/10 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
02Containers; Seals
10characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
H01L 23/48 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
CPC
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/05098
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05075Plural internal layers
0508being stacked
05085with additional elements, e.g. vias arrays, interposed between the stacked layers
05098Material of the additional element
H01L 2224/05186
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
05186with a principal constituent of the material being a non metallic, non metalloid inorganic material
H01L 2224/08145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08135the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
08145the bodies being stacked
H01L 2224/13025
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
1302Disposition
13025the bump connector being disposed on a via connection of the semiconductor or solid-state body
H01L 2224/131
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Applicants
  • RAMBUS INC. [US]/[US] (AllExceptUS)
  • FRANZON, Paul, Damian [US]/[US] (UsOnly)
  • WILSON, John (UsOnly)
Inventors
  • FRANZON, Paul, Damian
  • WILSON, John
Agents
  • KREISMAN, Lance, M.
Priority Data
61/407,84828.10.2010US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) THERMAL ISOLATION IN 3D CHIP STACKS USING GAP STRUCTURES AND CONTACTLESS COMMUNICATIONS
(FR) ISOLATION THERMIQUE DANS DES EMPILEMENTS DE PUCE TRIDIMENSIONNELS AU MOYEN DE STRUCTURES DE SÉPARATION ET DE COMMUNICATIONS SANS CONTACT
Abstract
(EN)
A semiconductor package is disclosed. The semiconductor package includes a first semiconductor device having a first contactless signaling interface; and a second semiconductor device. The second semiconductor device has a second contactless signaling interface to electrically communicate with the first contactless signaling interface. The second semiconductor device is formed with a gap disposed proximate the second contactless signaling interface.
(FR)
La présente invention concerne un boîtier pour semi-conducteurs. Le boîtier pour semi-conducteurs comprend un premier dispositif à semi-conducteurs comportant une première interface de signalisation sans contact, ainsi qu'un second dispositif à semi-conducteurs. Le second dispositif à semi-conducteurs comporte une seconde interface de signalisation sans contact pour communiquer électriquement avec la première interface de signalisation sans contact. Le second dispositif à semi-conducteurs est formé avec une séparation disposée à proximité de la seconde interface de signalisation sans contact.
Latest bibliographic data on file with the International Bureau