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1. WO2012055144 - TRANSISTOR AND MANUFACTURING METHOD THEREOF

Publication Number WO/2012/055144
Publication Date 03.05.2012
International Application No. PCT/CN2011/000280
International Filing Date 23.02.2011
IPC
H01L 21/425 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
42Bombardment with radiation
423with high-energy radiation
425producing ion implantation
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 29/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
CPC
H01L 21/26506
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26Bombardment with radiation
263with high-energy radiation
265producing ion implantation
26506in group IV semiconductors
H01L 21/26513
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26Bombardment with radiation
263with high-energy radiation
265producing ion implantation
26506in group IV semiconductors
26513of electrically active species
H01L 21/823807
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823807with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
H01L 21/823814
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823814with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
H01L 29/04
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
04characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/32
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
30characterised by physical imperfections; having polished or roughened surface
32the imperfections being within the semiconductor body
Applicants
  • 中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN]/[CN] (AllExceptUS)
  • 尹海洲 YIN, Haizhou [CN]/[US] (UsOnly)
  • 骆志炯 LUO, Zhijiong [CN]/[US] (UsOnly)
  • 朱慧珑 ZHU, Huilong [US]/[US] (UsOnly)
Inventors
  • 尹海洲 YIN, Haizhou
  • 骆志炯 LUO, Zhijiong
  • 朱慧珑 ZHU, Huilong
Agents
  • 中国专利代理(香港)有限公司 CHINA PATENT AGENT (H.K.) LTD.
Priority Data
201010532061.429.10.2010CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) TRANSISTOR AND MANUFACTURING METHOD THEREOF
(FR) TRANSISTOR ET SON PROCÉDÉ DE FABRICATION
(ZH) 晶体管及其制造方法
Abstract
(EN)
A transistor and a manufacturing method thereof are provided. The transistor (100) includes: a semiconductor substrate (102); a gate dielectric (104) formed on the semiconductor substrate; a gate (106) formed on the gate dielectric; a channel region (112) located under the gate dielectric; a source region (108) and a drain region (110) located in the semiconductor and respectively at both sides of the gate, wherein only the source region includes at least one dislocation (101). The manufacturing method of the transistor includes that: forming a mask layer (114) on the semiconductor substrate on which the gate is formed, wherein the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least one portion of the source region; performing a first ion implantation to the exposed portion of the source region; and performing an annealing to the semiconductor substrate to form the dislocation in the exposed portion of the source region.
(FR)
L'invention concerne un transistor et son procédé de fabrication. Le transistor (100) comprend : un substrat semi-conducteur (102) ; un diélectrique de grille (104) formé sur le substrat semi-conducteur ; une grille (106) formée sur le diélectrique de grille ; une région de canal (112) située sous le diélectrique de grille ; et une région de source (108) et une région de drain (110) situées dans le semi-conducteur et respectivement des deux côtés de la grille, la région de source uniquement comprenant au moins une dislocation (101). Le procédé de fabrication du transistor consiste à former une couche de masque (114) sur le substrat semi-conducteur sur lequel est formée la grille, la couche de masque recouvrant la grille et le substrat semi-conducteur ; modeler la couche de masque pour exposer uniquement au moins une partie de la région de source ; effectuer une première implantation ionique dans la partie exposée de la région de source ; et réaliser un recuit du substrat semi-conducteur pour former la dislocation dans la partie exposée de la région de source.
Also published as
Latest bibliographic data on file with the International Bureau