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Machine translation
1. (WO2012054711) POWER/GROUND LAYOUT FOR CHIPS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/054711    International Application No.:    PCT/US2011/057069
Publication Date: 26.04.2012 International Filing Date: 20.10.2011
IPC:
H01L 23/522 (2006.01), H01L 23/528 (2006.01), H01L 25/065 (2006.01), H01L 23/50 (2006.01), H01L 21/98 (2006.01)
Applicants: MARVELL WORLD TRADE LTD. [BB/BB]; L'horizon, Gunsite Road, Brittons Hill St.Michael, BB14027 (BB) (For All Designated States Except US).
SUTARDJA, Sehat [US/US]; (US) (For US Only).
HAN, Chung, Chyung [US/US]; (US) (For US Only).
LI, Weidan [US/US]; (US) (For US Only).
YU, Shuhua [--/US]; (US) (For US Only).
CHENG, Chuan-cheng [US/US]; (US) (For US Only).
WU, Albert [US/US]; (US) (For US Only)
Inventors: SUTARDJA, Sehat; (US).
HAN, Chung, Chyung; (US).
LI, Weidan; (US).
YU, Shuhua; (US).
CHENG, Chuan-cheng; (US).
WU, Albert; (US)
Agent: LEMOND, Kevin, T.; Lee & Hayes, PLLC 601 W. Riverside Ave, Suite 1400 Spokane, WA 99201 (US)
Priority Data:
13/277,140 19.10.2011 US
61/405,099 20.10.2010 US
Title (EN) POWER/GROUND LAYOUT FOR CHIPS
(FR) CONFIGURATION COURANT/TERRE POUR PUCES
Abstract: front page image
(EN)Embodiments of the present disclosure provide a chip that comprises a base metal layer (102) formed over a first semiconductor die (104) and a first metal layer (110) formed over the base metal layer. The first metal layer includes a plurality of islands (112) configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer (118) formed over the first metal layer. The second metal layer includes a plurality of islands (120) configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
(FR)Des modes de réalisation de la présente invention concernent une puce comprenant une couche métallique de base formée au-dessus d'un premier dé de semi-conducteur et une première couche métallique formée au-dessus de la couche métallique de base. La première couche métallique comprend plusieurs îlots configurés pour acheminer (i) un signal de terre ou (ii) un signal de courant dans la puce. La puce comprend en outre une seconde couche métallique formée au-dessus de la première couche métallique. La seconde couche métallique comprend plusieurs îlots configurés pour acheminer (i) le signal de terre ou (ii) le signal de courant dans la puce.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)