WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2012051281) AN INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/051281    International Application No.:    PCT/US2011/055943
Publication Date: 19.04.2012 International Filing Date: 12.10.2011
IPC:
G06F 9/30 (2006.01), G06F 9/305 (2006.01), G06F 9/06 (2006.01)
Applicants: SOFT MACHINES, INC. [US/US]; 3211 Scott Boulevard, Suite 202 Santa Clara, CA 95054 (US) (For All Designated States Except US).
ABDALLAH, Mohammad [US/US]; (US) (For US Only)
Inventors: ABDALLAH, Mohammad; (US)
Agent: BARNES, Glenn D.; Murabito Hao & Barnes LLP Two North Market Street Third Floor San Jose, CA 95113 (US)
Priority Data:
61/392,392 12.10.2010 US
Title (EN) AN INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES
(FR) TAMPON POUR SÉQUENCE D'INSTRUCTIONS DESTINÉ À STOCKER DES BRANCHEMENTS AYANT DES SÉQUENCEURS D'INSTRUCTIONS PRÉVISIBLES DE MANIÈRE FIABLE
Abstract: front page image
(EN)A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.
(FR)L'invention concerne un procédé destiné à délivrer des séquences d'instructions prévisibles de manière fiable. Le procédé consiste à effectuer un suivi d'occurrences répétitives pour déterminer un ensemble de séquences d'instructions à forte occurrence pour un microprocesseur et, à partir de cet ensemble, identifier une instruction de branchement ayant une série d'instructions de branchement ultérieures exécutées fréquemment qui forment une séquence d'instructions prévisible de manière fiable. La séquence d'instructions prévisible de manière fiable est stockée dans un tampon. Lors d'une occurrence ultérieure de l'instruction de branchement, la séquence d'instructions prévisible de manière fiable est fournie en sortie du tampon.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)