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1. (WO2012050322) METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL- STRUCTURE MEMORY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/050322    International Application No.:    PCT/KR2011/007403
Publication Date: 19.04.2012 International Filing Date: 06.10.2011
IPC:
H01L 21/8247 (2006.01), H01L 27/115 (2006.01), H01L 21/3065 (2006.01)
Applicants: EUGENE TECHNOLOGY CO., LTD. [KR/KR]; 209-3 Chugye-ri Yangji-myeon, Cheoin-gu, Yongin-si Gyeonggi-do 449-824 (KR) (For All Designated States Except US).
CHO, Sung Kil [KR/KR]; (KR) (For US Only).
KIM, Hai Won [KR/KR]; (KR) (For US Only).
WOO, Sang Ho [KR/KR]; (KR) (For US Only).
SHIN, Seung Woo [KR/KR]; (KR) (For US Only).
JANG, Gil Sun [KR/KR]; (KR) (For US Only).
OH, Wan Suk [KR/KR]; (KR) (For US Only)
Inventors: CHO, Sung Kil; (KR).
KIM, Hai Won; (KR).
WOO, Sang Ho; (KR).
SHIN, Seung Woo; (KR).
JANG, Gil Sun; (KR).
OH, Wan Suk; (KR)
Agent: JEONG, Seong Jin; (2nd Floor, Ace High-End Tower 3, Gasan-Dong) Rm. 204, 145 Gasan Digital 1-ro Gumchun-gu, Seoul 153-787 (KR)
Priority Data:
10-2010-0100093 14.10.2010 KR
Title (EN) METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL- STRUCTURE MEMORY DEVICE
(FR) PROCÉDÉ ET DISPOSITIF DE FABRICATION DE DISPOSITIF DE MÉMOIRE À STRUCTURE TRIDIMENSIONNELLE
(KO) 3차원 구조의 메모리 소자를 제조하는 방법 및 장치
Abstract: front page image
(EN)A method for manufacturing a memory device having a three-dimensional structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for evaporating a silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, and the step for laminating the sacrificial layer includes a step for evaporating a nitride film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and SiCl2H2, and a gas from the ammonia series.
(FR)La présente invention concerne un procédé de fabrication d'un dispositif de mémoire présentant une structure tridimensionnelle. Selon un mode de réalisation de l'invention, ce procédé comporte les étapes suivantes: une étape par laquelle on stratifie en alternance sur le substrat une ou plusieurs couches d'isolation et une ou plusieurs couches sacrificielles; une étape par laquelle on réalise un trou de pénétration permettant de pénétrer dans la couche d'isolation et dans la couche sacrificielle; une étape par laquelle on réalise un motif destiné à combler le trou de pénétration; une étape par laquelle on réalise une ouverture permettant de pénétrer dans la couche d'isolation et dans la couche sacrificielle; et une étape par laquelle, pour enlever la couche sacrificielle, on fait arriver par l'ouverture un agent de gravure. En outre, l'étape de stratification de la couche d'isolation comporte une étape par laquelle, pour faire évaporer une pellicule d'oxyde de silicium, on fait arriver sur le substrat au moins un gaz choisi dans le groupe constitué des SiH4, Si2H6, Si3H8, et Si4H10. Enfin, l'étape de stratification de la couche sacrificielle comporte une étape par laquelle, pour faire évaporer une pellicule de nitrure, on fait arriver sur le substrat un gaz choisi dans le groupe constitué des SiH4, Si2H6, Si3H8, Si4H10, et SiCl2H2, et un gaz de la famille des ammoniums.
(KO)본 발명의 일 실시예에 의하면, 3차원 구조의 메모리 소자를 제조하는 방법은 기판 상에 하나 이상의 절연층 및 하나 이상의 희생층을 교대로 적층하는 단계; 상기 절연층 및 상기 희생층을 관통하는 관통홀을 형성하는 단계; 상기 관통홀을 채우는 패턴을 형성하는 단계; 상기 절연층 및 상기 희생층을 관통하는 개구를 형성하는 단계; 그리고 상기 개구를 통해 에천트를 공급하여 상기 희생층을 제거하는 단계를 포함하되, 상기 절연층을 적층하는 단계는 상기 기판에 SiH4, Si2H6, Si3H8, Si4H10을 포함하는 군으로부터 선택된 하나 이상의 가스를 공급하여 실리콘 산화막을 증착하는 단계를 포함하며, 상기 희생층을 적층하는 단계는 상기 기판에 SiH4, Si2H6, Si3H8, Si4H10, SiCl2H2을 포함하는 군으로부터 선택된 하나 이상의 가스와 암모니아 계열의 가스를 공급하여 질화막을 증착하는 단계를 포함한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)