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1. (WO2012045257) VERTICAL CHANNEL FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2012/045257    International Application No.:    PCT/CN2011/079521
Publication Date: 12.04.2012 International Filing Date: 09.09.2011
IPC:
H01L 29/78 (2006.01), H01L 21/336 (2006.01)
Applicants: PEKING UNIVERSITY [CN/CN]; No.5 Yiheyuan Road Haidian District Beijing 100871 (CN) (For All Designated States Except US).
HUANG, Ru [CN/CN]; (CN) (For US Only).
AI, Yujie [CN/CN]; (CN) (For US Only).
HAO, Zhihua [CN/CN]; (CN) (For US Only).
PU, Shuangshuang [CN/CN]; (CN) (For US Only).
FAN, Jiewen [CN/CN]; (CN) (For US Only).
SUN, Shuai [CN/CN]; (CN) (For US Only).
WANG, Runsheng [CN/CN]; (CN) (For US Only).
XU, Xiaoyan [CN/CN]; (CN) (For US Only)
Inventors: HUANG, Ru; (CN).
AI, Yujie; (CN).
HAO, Zhihua; (CN).
PU, Shuangshuang; (CN).
FAN, Jiewen; (CN).
SUN, Shuai; (CN).
WANG, Runsheng; (CN).
XU, Xiaoyan; (CN)
Agent: CHINABLE IP; 620 Room, 35-10-2, the 6th floor, No.35 Anding Road, Chaoyang District Beijing 100029 (CN)
Priority Data:
201010506129.1 09.10.2010 CN
Title (EN) VERTICAL CHANNEL FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
(FR) TRANSISTOR À EFFET DE CHAMP À CANAL VERTICAL ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种垂直沟道场效应晶体管及其制备方法
Abstract: front page image
(EN)A vertical channel field effect transistor and the manufacturing method thereof are provided. A channel region of the field effect transistor is a Si nanoring ( 207) perpendicular to the silicon (Si) substrate ( 201); the source terminal is source terminal polysilicon (205) and is located on the upper end of the Si nanoring (207 ); a drain region (212) is located outside of bottom end of the Si nanoring ( 207 ); a gate polysilicon (211 ) is located outside of the Si nanoring ( 207); a filling dielectric (208) is inside the Si nanoring ( 207 ). The ring structure field effect transistor of the invention can effectively suppress short channel effect.
(FR)La présente invention concerne un transistor à effet de champ à canal vertical et son procédé de fabrication. Une région de canal du transistor à effet de champ est un nano-anneau de Si (207) perpendiculaire au substrat de silicium (Si) (201) ; le terminal source est un polysilicium de terminal source (205) situé sur l'extrémité supérieure du nano-anneau de Si (207) ; une région de drain (212) se situe en dehors de l'extrémité inférieure du nano-anneau de Si (207) ; un polysilicium de porte (211) se situe en dehors du nano-anneau de Si (207) ; le diélectrique (208) est rempli à l'intérieur du nano-anneau de Si (207). Le transistor à effet de champ à structure en anneau de l'invention peut efficacement supprimer l'effet de canal court.
(ZH)一种垂直沟道场效应晶体管及其制备方法。该场效应晶体管的沟道区为垂直于硅(Si)衬底(201)上的Si纳米环(207);源端为源端多晶硅(205),位于Si纳米环(207)的上端;漏区(212)位于Si纳米环(207)下端的外侧;栅极多晶硅(211)位于Si纳米环(207)的外侧面;在Si纳米环(207)的内部有填充介质(208)。本发明的圆环结构场效应晶体管可有效抑制短沟效应。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)