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1. (WO2011159419) BIPOLAR TRANSISTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE

Pub. No.:    WO/2011/159419    International Application No.:    PCT/US2011/036729
Publication Date: Dec 22, 2011 International Filing Date: May 17, 2011
IPC: H01L 21/331
H01L 29/10
H01L 29/732
H01L 29/737
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
CAMILLO-CASTILLO, Renata
DAHLSTROM, Mattias, E.
GRAY, Peter, B.
HARAME, David, L.
HERRIN, Russell, T.
JOSEPH, Alvin, J.
STRICKER, Andreas, D.
Inventors: CAMILLO-CASTILLO, Renata
DAHLSTROM, Mattias, E.
GRAY, Peter, B.
HARAME, David, L.
HERRIN, Russell, T.
JOSEPH, Alvin, J.
STRICKER, Andreas, D.
Title: BIPOLAR TRANSISTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE
Abstract:
Disclosed are embodiments of an improved transistor structure (100) (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure (100). The structure embodiments can incorporate a dielectric layer (130) sandwiched between an intrinsic base layer (120) and a raised extrinsic base layer (140) to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap (150) for an intrinsic base layer (120) to extrinsic base layer (140) link-up region to reduce base resistance Rb and a dielectric spacer (160) between the extrinsic base layer (140) and an emitter layer (180) to reduce base- emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer (130), the width of the conductive strap (150), the width of the dielectric spacer (160) and the width of the emitter layer (180)) to be selectively adjusted in order to optimize transistor performance.