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Machine translation
1. (WO2011157571) STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/157571    International Application No.:    PCT/EP2011/059176
Publication Date: 22.12.2011 International Filing Date: 02.06.2011
IPC:
H01L 21/336 (2006.01), H01L 29/786 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504 (US) (For All Designated States Except US).
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU (GB) (MG only).
SHAHIDI, Ghavam [IR/US]; (US) (For US Only).
DORIS, Bruce [US/US]; (US) (For US Only).
KHAKIFIROOZ, Ali [IR/US]; (US) (For US Only).
KULKARNI, Pranita [IN/US]; (US) (For US Only).
CHENG, Kangguo [CN/US]; (US) (For US Only)
Inventors: SHAHIDI, Ghavam; (US).
DORIS, Bruce; (US).
KHAKIFIROOZ, Ali; (US).
KULKARNI, Pranita; (US).
CHENG, Kangguo; (US)
Agent: LITHERLAND, David, Peter; IBM United Kingdom Limited Intellectual Property Law Hursley Park Winchester Hampshire SO21 2JN (GB)
Priority Data:
12/816,399 16.06.2010 US
Title (EN) STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER
(FR) DISPOSITIF CMOS CONTRAINT À CORPS MINCE AYANT DES STRESSEURS DE SOURCE/DRAIN DRESSÉS VERTICALEMENT ET UNE COUCHE D'ESPACEMENT UNIQUE
Abstract: front page image
(EN)A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
(FR)L'invention concerne un procédé de formation d'un dispositif à transistor, comprenant les étapes suivantes : former une structure de grille gravée sur un substrat semi-conducteur ; former une couche d'espacement sur le substrat semi-conducteur et la structure de grille gravée ; éliminer des parties disposées horizontalement de la couche d'espacement, afin de former une paroi latérale verticale d'espacement adjacente à la structure de grille gravée ; et former une structure de source/drain dressée (RSD) sur le substrat semi-conducteur et adjacente à la paroi latérale verticale d'espacement. La structure RSD offre un profil latéral substantiellement vertical, afin de venir en butée contre la paroi latérale verticale d'espacement et de produire une contrainte de traction ou de compression sur une région de canal du substrat semi-conducteur, au-dessous de la structure de grille gravée.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)