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1. WO2011156787 - PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD

Publication Number WO/2011/156787
Publication Date 15.12.2011
International Application No. PCT/US2011/040090
International Filing Date 10.06.2011
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H01L 21/8247 (2006.01)
H01L 27/115 (2006.01)
CPC
H01L 27/2463
H01L 45/085
H01L 45/1233
H01L 45/148
H01L 45/1608
H01L 45/1616
Applicants
  • CROSSBAR, INC. [US/US]; 3200 Patrick Henry Drive, Suite 110 Santa Clara, CA 95054, US (AllExceptUS)
  • HERNER, Scott, Brad [US/US]; US (UsOnly)
Inventors
  • HERNER, Scott, Brad; US
Agents
  • CHO, Steve, Y.; Ampacc Law Group, PLLC 6100 219th Street Sw, Ste 580 Mountlake Terrace, WA 98053, US
Priority Data
61/354,16611.06.2010US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD
(FR) STRUCTURE DE PILIER POUR DISPOSITIF DE MÉMOIRE ET PROCÉDÉ
Abstract
(EN)
A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
(FR)
L'invention porte sur un procédé de formation d'un dispositif de mémoire. Le procédé utilise un substrat semi-conducteur ayant une région de surface. Une première couche diélectrique est formée, sus-jacente à la région de surface du substrat semi-conducteur. Une structure de câblage inférieure est formée, sus-jacente à la première couche diélectrique, et un second matériau diélectrique est formé, sus-jacent à la couche de câblage supérieure. Un matériau de barrière métallique inférieure est formé de façon à produire un contact métal-métal avec la structure de câblage inférieure. Le procédé forme une structure de pilier en exécutant un motif et une gravure d'un empilement de matériaux comprenant le matériau de barrière métallique inférieure, un matériau de contact, un matériau de commutation, un matériau conducteur et un matériau de barrière supérieure. La structure de pilier maintient un contact métal-métal avec la structure de câblage inférieure quel que soit l'alignement de la structure de pilier avec la structure de câblage inférieure pendant la gravure. Une structure de câblage supérieure est formée, sus-jacente à la structure de pilier selon un certain angle par rapport à la structure de câblage inférieure.
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