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1. WO2011156285 - SYSTEMS AND METHODS FOR DYNAMIC MULTI-LINK COMPILATION PARTITIONING

Publication Number WO/2011/156285
Publication Date 15.12.2011
International Application No. PCT/US2011/039310
International Filing Date 06.06.2011
IPC
G06F 13/14 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
G06F 1/32 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
26Power supply means, e.g. regulation thereof
32Means for saving power
CPC
G06F 1/32
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
G06F 13/14
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
G06F 13/409
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4063Device-to-bus coupling
409Mechanical coupling
G09G 5/006
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
003Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
006Details of the interface to the display terminal
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants
  • SULLIVAN, Jason A. [US]/[US]
Inventors
  • SULLIVAN, Jason A.
Agents
  • TINGEY, David B.
Priority Data
13/153,18903.06.2011US
61/352,35107.06.2010US
61/352,36307.06.2010US
61/352,36807.06.2010US
61/352,37207.06.2010US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEMS AND METHODS FOR DYNAMIC MULTI-LINK COMPILATION PARTITIONING
(FR) SYSTÈMES ET PROCÉDÉS DE PARTITIONNEMENT DE COMPILATION MULTI-LIAISON DYNAMIQUE
Abstract
(EN) Systems and methods for dynamic multi-link compilation partitioning. In particular, some implementations of the present invention relate to systems and methods for connecting a computer processing unit to a video display through the use of a wide variety of video display connectors. The present invention further relates to a dynamic interface incorporating USB, PCI-express, SATA, I2C, and power management bus (PMBus) technologies. Further still, some implementations of the present invention relate to an openly connected dynamic storage system whereby the storage capacity of a processing unit is increased by coupling additional storage components to the processing unit via a dynamic interface connector that is interposedly connected. Some implementations of the invention further relate to a customizable grouping of PCIe lanes to provide for a flexible allocation of the lanes to customize the characteristic of the board set, while reducing the power consumption, improving the bandwidth and speed of the device, reducing the cost of the device and providing serial data transfer architecture to provide multiple busses.
(FR) L'invention porte sur des systèmes et des procédés de partitionnement de compilation multi-liaison dynamique. En particulier, certaines mises en œuvre de la présente invention portent sur des systèmes et des procédés de connexion d'une unité de traitement informatique à un écran vidéo par utilisation d'une grande diversité de connecteurs d'écran vidéo. La présente invention porte en outre sur une interface dynamique incorporant des technologies USB, PCI-express, SATA, I²C, et de bus de gestion d'énergie (PMBus). En outre, certaines mises en œuvre de la présente invention portent sur un système de stockage dynamique connecté de manière ouverte qui permet d'augmenter la capacité de stockage d'une unité de traitement par couplage de composants de stockage supplémentaires à l'unité de traitement par l'intermédiaire d'un connecteur d'interface dynamique qui est connecté intercalé. Certaines mises en œuvre de l'invention portent en outre sur un regroupement personnalisable de voies PCIe pour permettre une affectation flexible des voies afin de personnaliser la caractéristique de l'ensemble de cartes, tout en réduisant la consommation d'énergie, en améliorant la bande passante et la vitesse du dispositif, en réduisant le coût du dispositif et en fournissant une architecture de transfert de données série pour permettre de multiples bus.
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