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Machine translation
1. (WO2011149768) SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/149768    International Application No.:    PCT/US2011/037275
Publication Date: 01.12.2011 International Filing Date: 20.05.2011
IPC:
H01L 29/78 (2006.01), H01L 21/336 (2006.01)
Applicants: SS SC IP, LLC [US/US]; 1401 Livingston Lane Jackson, MS 39213 (US) (For All Designated States Except US).
RITENOUR, Andrew [US/US]; (US) (For US Only).
SHERIDAN, David C. [US/US]; (US) (For US Only)
Inventors: RITENOUR, Andrew; (US).
SHERIDAN, David C.; (US)
Agent: RAIMUND, Christopher W.; 1333 H Street, NW Suite 820 Washington, District of Columbia 20005 (US)
Priority Data:
61/347,928 25.05.2010 US
Title (EN) SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING
(FR) DISPOSITIFS SEMI-CONDUCTEURS AUTO-ALIGNÉS À FUITE GRILLE-SOURCE RÉDUITE SOUS UNE POLARISATION INVERSÉE, AINSI QUE PROCÉDÉS DE FABRICATION
Abstract: front page image
(EN)A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self- aligned to within 0.5 um to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.
(FR)L'invention concerne un transistor à effet de champ à jonction verticale (VJFET) ayant une broche auto-alignée et une jonction grille-source p+/n/n+ ou p+/p/n+. La grille du dispositif peut être auto-alignée avec une tolérance de 0,5 µm avec la source afin de préserver de bonnes performances en haute tension (c'est-à-dire à faible DIBL) tout en réduisant la fuite de la jonction grille-source sous une polarisation inversée. Le dispositif peut être un dispositif semi-conducteur à bande interdite large tel qu'un transistor à effet de champ à jonction verticale SiC. L'invention concerne en outre des procédés de fabrication du dispositif.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)