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1. (WO2011148658) SCANNING SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE PROVIDED WITH SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2011/148658 International Application No.: PCT/JP2011/050782
Publication Date: 01.12.2011 International Filing Date: 18.01.2011
IPC:
G09G 3/36 (2006.01) ,G09G 3/20 (2006.01) ,G11C 19/00 (2006.01) ,G11C 19/28 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
19
Digital stores in which the information is moved stepwise, e.g. shift registers
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
19
Digital stores in which the information is moved stepwise, e.g. shift registers
28
using semiconductor elements
Applicants:
高橋 佳久 TAKAHASHI, Yoshihisa; null (UsOnly)
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府大阪市阿倍野区長池町22番22号 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
Inventors:
高橋 佳久 TAKAHASHI, Yoshihisa; null
Agent:
島田 明宏 SHIMADA, Akihiro; 奈良県橿原市八木町1丁目10番3号 萬盛庵ビル 島田特許事務所 Shimada Patent Firm, Manseian Building, 1-10-3, Yagi-cho, Kashihara-shi, Nara 6340078, JP
Priority Data:
2010-11826124.05.2010JP
Title (EN) SCANNING SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE PROVIDED WITH SAME
(FR) CIRCUIT D'ATTAQUE DE LIGNE DE SIGNAL DE BALAYAGE ET DISPOSITIF D'AFFICHAGE LE COMPORTANT
(JA) 走査信号線駆動回路およびそれを備えた表示装置
Abstract:
(EN) Provided is a monolithic gate driver that operates with relatively few circuit elements. A component circuit constituting each stage of a shift register comprises: two output terminals (61, 62) connected to a scanning signal line; two thin-film transistors (MA1, MB1) in which an output control clock signal is provided to drain terminals, and source terminals are connected to the output terminals; a first node (N1) connected to the two thin-film transistors (MA1, MB1); a first node control circuit (420); and an input terminal (41) that receives a set signal (S). In a configuration such as this, the first node (N1) changes from an off-level to an on-level on the basis of the set signal (S). The first node control circuit (420) changes the first node (N1) from an on-level to an off-level.
(FR) L'invention concerne un circuit d'attaque de grille monolithique qui fonctionne avec un nombre relativement faible d'éléments de circuit. Un circuit constitutif constituant chaque étage d'un registre à décalage comprend : deux bornes de sortie (61, 62) connectées à une ligne de signal de balayage ; deux transistors à couches minces (MA1, MB1) à des bornes de drain desquels est fourni un signal d'horloge de commande de sortie, et des bornes de source sont connectées aux bornes de sortie ; un premier nœud (N1) connecté aux deux transistors à couches minces (MA1, MB1) ; un premier circuit de commande de nœud (420) ; et une borne de sortie (41) qui reçoit un signal de positionnement (S). Dans une configuration telle que celle-ci, le premier nœud (N1) passe d'un niveau non passant à un niveau passant en fonction du signal de positionnement (S). Le premier circuit de commande de nœud (420) fait passer le premier nœud (N1) d'un niveau passant à un niveau non passant.
(JA)  比較的少ない回路素子で動作するモノリシックゲートドライバを実現する。 シフトレジスタの各段を構成する段構成回路は、走査信号線に接続された2個の出力端子(61,62)と、出力制御用クロック信号がドレイン端子に与えられ出力端子にソース端子が接続された2個の薄膜トランジスタ(MA1,MB1)と、2個の薄膜トランジスタ(MA1,MB1)に共通的に接続された第1ノード(N1)と、第1ノード制御回路(420)と、セット信号(S)を受け取る入力端子(41)とを含む。このような構成において、第1ノード(N1)は、セット信号(S)に基づいてオフレベルからオンレベルへと変化する。また、第1ノード制御回路(420)は、第1ノード(N1)をオンレベルからオフレベルへと変化させる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)