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Machine translation
1. (WO2011142582) STACKED SEMICONDUCTOR PACKAGE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/142582    International Application No.:    PCT/KR2011/003468
Publication Date: 17.11.2011 International Filing Date: 11.05.2011
IPC:
H01L 23/12 (2006.01)
Applicants: HANA MICRON INC. [KR/KR]; 95-1, Wonnam-ri, Eumbong-myeon Asan-si, Chungcheongnam-do 336-864 (KR) (For All Designated States Except US).
HWANG, Chul Kyu [KR/KR]; (KR) (For US Only).
LEE, Hyun Woo [KR/KR]; (KR) (For US Only)
Inventors: HWANG, Chul Kyu; (KR).
LEE, Hyun Woo; (KR)
Agent: LEEON INTELLECTUAL PROPERTY LAW FIRM; 316, Kolon Science Valley 2cha 811, Guro-dong, Guro-gu Seoul 152-050 (KR)
Priority Data:
10-2010-0043637 10.05.2010 KR
Title (EN) STACKED SEMICONDUCTOR PACKAGE
(FR) BOÎTIER POUR SEMICONDUCTEURS EMPILÉS
(KO) 적층형 반도체 패키지
Abstract: front page image
(EN)Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate unit, which includes a connection substrate electrically connecting a first substrate having a contact pad and a second substrate having a contact pad; a first chip laminate at which a plurality of first semiconductor chips are stacked in multi-steps on the first substrate; a second chip laminate at which a plurality of second semiconductor chips are stacked in multi-steps on the second substrate; a first conductive wire which electrically connects a first bonding pad of the first semiconductor chip and the contact pad of the first substrate, a second conductive wire which electrically connects a second bonding pad of the second semiconductor chip and the contact pad of the second substrate, and a bonding unit which has a contact adhesive layer having a certain thickness, which is disposed between the first semiconductor chip in the top layer of the first chip laminate and the second semiconductor chip in the top layer of the second chip laminate, and which vertically stacks and bonds the first chip laminate and the second chip laminate.
(FR)L'invention concerne un boîtier pour semiconducteurs empilés. Le boîtier pour semiconducteurs empilés selon la présente invention comprend : une unité de substrat qui comprend un substrat de connexion qui connecte électriquement un premier substrat ayant une pastille de contact et un second substrat ayant une pastille de contact; une première stratification de puces, dans laquelle une pluralité de premières puces semiconductrices sont empilées en formant des étages multiples sur le premier substrat; une seconde stratification de puces, dans laquelle une pluralité de secondes puces semiconductrices sont empilées en formant des étages multiples sur le second substrat; un premier fil conducteur qui connecte électriquement une première pastille de raccordement de la première puce semiconductrice et la pastille de contact du premier substrat; un second fil conducteur qui connecte électriquement une seconde pastille de raccordement de la seconde puce semiconductrice et la pastille de contact du second substrat; et une unité de collage qui comprend une couche d'adhésif de contact ayant une certaine épaisseur et qui est disposée entre la première puce semiconductrice, dans la couche supérieure de la première stratification de puces, et la seconde puce semiconductrice, dans la couche supérieure de la seconde stratification de puces, et qui empile et colle verticalement la première stratification de puces et la seconde stratification de puces.
(KO)적층형 반도체 패키지를 제공한다. 본 발명은 접속패드를 갖는 제1기판과 접속패드를 갖는 제2기판사이를 전기적으로 연결하는 연결기판을 구비하는 기판부; 상기 제1기판상에 복수개의 제1반도체칩이 다단으로 적층되는 제1칩적층체; 상기 제2기판상에 복수개의 제2반도체칩이 다단으로 적층되는 제2칩적층체; 상기 제1반도체칩의 제1본딩패드와 상기 제1기판의 접속패드를 전기적으로 연결하는 제1도전성 와이어; 상기 제2반도체칩의 제2본딩패드와 상기 제2기판의 접속패드를 전기적으로 연결하는 제2도전성 와이어; 및 상기 제1집적층체의 최상층 제1반도체칩과 상기 제2칩적층체의 최상층 제2반도체칩사이에 개재되는 일정두께의 연결접착층을 갖추어 상기 제1칩적층체와 제2칩적층체를 상하 적층하여 접합하는 접합부를 포함한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)