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Machine translation
1. (WO2011140515) LINKED -LIST MANAGEMENT OF LLR- MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/140515    International Application No.:    PCT/US2011/035638
Publication Date: 10.11.2011 International Filing Date: 06.05.2011
IPC:
H04L 1/00 (2006.01), H04L 1/18 (2006.01)
Applicants: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 (US) (For All Designated States Except US).
FUCHS, Robert Jason [CA/US]; (US) (For US Only).
KONGELF, Robert, Jason [US/US]; (US) (For US Only).
THELEN, Christian, D. [DE/US]; (US) (For US Only).
DHAWAN, Rajat, R. [US/US]; (US) (For US Only).
XU, Hao [US/US]; (US) (For US Only)
Inventors: FUCHS, Robert Jason; (US).
KONGELF, Robert, Jason; (US).
THELEN, Christian, D.; (US).
DHAWAN, Rajat, R.; (US).
XU, Hao; (US)
Agent: VU, Kenneth, K., D.; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 (US)
Priority Data:
61/332,580 07.05.2010 US
13/101,947 05.05.2011 US
Title (EN) LINKED -LIST MANAGEMENT OF LLR- MEMORY
(FR) GESTION DE LISTE CHAÎNÉE DE MÉMOIRE LLR
Abstract: front page image
(EN)Certain aspects of the present disclosure relate to a method and apparatus for processing wireless communications. According to certain aspects, a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block is generated. Each chunk holds LLR values for a code block of the transport block. The linked list is then provided to a hardware circuit for traversal. According to certain aspects, the hardware circuit may be an application specific integrated circuit (ASIC) processor or field programmable gate array (FPGA) configured to traverse the linked list of chunks of memory used to store LLR values.
(FR)Certains aspects de la présente invention portent sur un procédé et sur un appareil de traitement de communications sans fil. Selon certains aspects, une liste chaînée de blocs de mémoire utilisés pour stocker des valeurs de logarithme du rapport de vraisemblance (LLR) pour un bloc de transport est générée. Chaque bloc contient des valeurs LLR pour un bloc de code (CB) du bloc de transport (TB). La liste chaînée est ensuite fournie à un circuit matériel pour la parcourir. Selon certains aspects, le circuit matériel peut être un processeur à circuit intégré à application spécifique (ASIC) ou un réseau prédiffusé programmable par l'utilisateur (FPGA) configuré pour parcourir la liste chaînée de blocs de mémoire utilisés pour stocker des valeurs LLR.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)