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Machine translation
1. (WO2011139000) DYNAMIC BIAS CURRENT-STARVED INVERTER AND LOW-POWER DELTA-SIGMA MODULATOR USING THE INVERTER
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/139000    International Application No.:    PCT/KR2010/003516
Publication Date: 10.11.2011 International Filing Date: 01.06.2010
IPC:
H03K 19/0948 (2006.01), H03F 3/70 (2006.01), H03F 3/45 (2006.01)
Applicants: SNU R&DB FOUNDATION [KR/KR]; San 56-1 Sillim-dong, Gwanak-gu Seoul 151-742 (KR) (For All Designated States Except US).
JEONG, Deog Kyoon [KR/KR]; (KR) (For US Only).
LEE, Sang Yoon [KR/KR]; (KR) (For US Only).
LIM, Dong Hyuk [KR/KR]; (KR) (For US Only).
CHOI, Woo Seok [KR/KR]; (KR) (For US Only)
Inventors: JEONG, Deog Kyoon; (KR).
LEE, Sang Yoon; (KR).
LIM, Dong Hyuk; (KR).
CHOI, Woo Seok; (KR)
Priority Data:
10-2010-0042733 07.05.2010 KR
Title (EN) DYNAMIC BIAS CURRENT-STARVED INVERTER AND LOW-POWER DELTA-SIGMA MODULATOR USING THE INVERTER
(FR) INVERSEUR DYNAMIQUE À INSUFFISANCE DE COURANT DE POLARISATION ET MODULATEUR DELTA-SIGMA DE FAIBLE PUISSANCE UTILISANT L'INVERSEUR
(KO) 동적 바이어스 작동하는 전류기근형 인버터 및 이를 이용한 저전력 델타 시그마 모듈레이터
Abstract: front page image
(EN)A bootstrap capacitor is installed between gates of a pair of cascade-connected PMOS transistors, and between gates of a pair of cascade-connected NMOS transistors, respectively. In a data sampling step (Φ1), all of the PMOS transistors and NMOS transistors are weakly inverted through current starvation such that charges corresponding to the potential differences between an input voltage (VIN) and reference voltages (VBP, VBN) are stored in a bootstrap capacitor. In a charge transfer step (Φ2A), the input voltage strongly inverts one of the NMOS transistor pair or the PMOS transistor pair according to polarity, and the remaining pair is cut off, thereby securing a broad bandwidth. Following the charge transfer, in a normal state step (Φ2B), all of the PMOS transistors and the NMOS transistors return to the weak inversion state so as to achieve a high gain and prevent power waste.
(FR)La présente invention concerne un condensateur auto-élévateur installé entre les grilles d'une paire de transistors PMOS connectés en cascade, et entre les grilles d'une paire de transistors NMOS connectés en cascade, respectivement. Lors d'une étape d'échantillonnage (Φ1), tous les transistors PMOS et transistors NMOS sont inversés faiblement par une insuffisance de courant de sorte que des charges correspondant aux différences de potentiel entre une tension d'entrée (VIN) et des tensions de référence (VBP, VBN) soient stockées dans un condensateur auto-élévateur. Lors d'une étape de transfert de charge (Φ2A), la tension d'entrée effectue une forte inversion d'une parmi la paire de transistors NMOS et la paire de transistors PMOS basée sur la polarité, et l'autre paire est bloquée, permettant ainsi l'obtention d'une large bande passante. Suite au transfert de charge, lors d'une étape normale (Φ2B), tous les transistors PMOS et transistors NMOS retournent vers l'état de faible inversion pour réaliser un gain élevé et empêcher le gaspillage d'énergie.
(KO)본 발명은 캐스코드 연결된 한 쌍의 PMOS 트랜지스터의 각각의 게이트 사이와, 캐스코드 연결된 한 쌍의 NMOS 트랜지스터의 각각의 게이트 사이에 부트스트랩 캐패시터를 설치하고, 데이터 샘플링 단계(Φ1)에서는 전류기근을 통해 PMOS 트랜지스터와 NMOS 트랜지스터를 모두 약반전 동작시켜 부트스트랩 캐패시터에 입력 전압(VIN)과 기준전압(VBP, VBN) 사이의 전위차에 대응된 전하를 저장하였다가, 전하전달 단계(Φ2A)에서는 입력전압이 극성에 따라 NMOS 트랜지스터 쌍 또는 PMOS 트랜지스터 쌍 중 어느 한 쌍을 강반전으로 구동하고 다른 한 쌍은 컷오프 동작하도록 하여 넓은 대역폭을 확보하도록 하고, 전하전달 후 정상상태 단계(Φ2B)에서는 PMOS 트랜지스터와 NMOS 트랜지스터를 모두 약반전 회귀시켜 높은 이득과 함께 전력소모를 방지하는 방식을 제공한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)