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1. WO2011132225 - PIN CARD AND TEST DEVICE USING SAME

Publication Number WO/2011/132225
Publication Date 27.10.2011
International Application No. PCT/JP2010/002900
International Filing Date 22.04.2010
IPC
G01R 31/28 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
H01L 21/66 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66Testing or measuring during manufacture or treatment
CPC
G01R 31/26
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26Testing of individual semiconductor devices
G01R 31/2841
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
2832Specific tests of electronic circuits not provided for elsewhere
2836Fault-finding or characterising
2839using signal generators, power supplies or circuit analysers
2841Signal generators
G01R 31/2851
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
2851Testing of integrated circuits [IC]
G01R 31/317
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
G01R 31/3183
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3183Generation of test inputs, e.g. test vectors, patterns or sequences
Applicants
  • 株式会社アドバンテスト ADVANTEST CORPORATION [JP]/[JP] (AllExceptUS)
  • 川原貴夫 KAWAHARA, Takao [JP]/[JP] (UsOnly)
  • 中村隆之 NAKAMURA, Takayuki [JP]/[JP] (UsOnly)
Inventors
  • 川原貴夫 KAWAHARA, Takao
  • 中村隆之 NAKAMURA, Takayuki
Agents
  • 森下賢樹 MORISHITA, Sakaki
Priority Data
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) PIN CARD AND TEST DEVICE USING SAME
(FR) CARTE À BROCHES ET DISPOSITIF DE TEST L'UTILISANT
(JA) ピンカードおよびそれを用いた試験装置
Abstract
(EN) A DUT (1) is connected to an I/O terminal (Pio). An AC test unit (30) performs an AC test on the DUT (1). A DC test unit (40) performs a DC test on the DUT (1). A first terminal (P1) of an optical semiconductor switch (10) is connected to the AC test unit (30), and a second terminal (P2) is connected to the I/O terminal (Pio). The optical semiconductor switch (10) is configured to enable switching between conductive and cut-off states between the first terminal (P1) and the second terminal (P2) according to a control signal input to control terminals (P3, P4). A first impedance circuit (20) is disposed on the control signal path of the positive electrode control terminal (P3), and a second impedance circuit (22) is disposed on the control signal path of the negative electrode terminal (P4).
(FR) Un dispositif à l'essai (1) est connecté à un terminal E/S (Pio). Une unité de test CA (30) effectue un test CA sur le dispositif à l'essai (1). Une unité de test CC (40) effectue un test CC sur le dispositif à l'essai (1). Une première borne (P1) d'un interrupteur semi-conducteur optique (10) est connectée à l'unité de test CA (30), et une deuxième borne (P2) est connectée au terminal E/S (Pio). L'interrupteur optique semi-conducteur (10) est configuré de façon à permettre la commutation entre un état conducteur et un état de coupure entre la première borne (P1) et la deuxième borne (P2) en fonction d'une entrée de signal de commande aux bornes de commande (P3, P4). Un premier circuit d'impédance (20) est placé sur le chemin du signal de commande de la borne de commande positive (P3) et un deuxième circuit d'impédance (22) est placé sur le chemin du signal de commande de la borne négative (P4).
(JA)  I/O端子Pioには、DUT1が接続される。交流試験ユニット30はDUT1の交流試験を行う。直流試験ユニット40はDUT1の直流試験を行う。光半導体スイッチ10の第1端子P1は交流試験ユニット30と接続され、第2端子P2はI/O端子Pioと接続される。光半導体スイッチ10は、制御端子P3、P4に入力される制御信号に応じて、第1端子P1と第2端子P2の間の導通、遮断状態が切りかえ可能に構成される。第1インピーダンス回路20は、正極制御端子P3に対する制御信号の信号経路に設けられ、第2インピーダンス回路22は、負極制御端子P4に対する制御信号の信号経路に設けられる。
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